JPS584459B2 - flip-flop circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter referred to as MI
The present invention relates to a memory cell circuit device configured with SFET (referred to as SFET).

In general, a flip-flop circuit composed of MISFETs has a power supply voltage applied to its gate electrode, and a load MISF circuit that uses the operating resistance in a conductive state as a load resistance.
This circuit has two inverting circuits in which an ET and a driving MISFET are connected in series, and the input terminal and output terminal of the inverting circuit are connected to each other.

When a memory cell is constructed by providing a transmission gate MISFET at the output terminal of each inverting circuit of the above-mentioned flip-flop circuit and used as a semiconductor storage device, the number of elements per bit is as large as 6, which results in poor integration. Moreover, since current always flows in one of the two inverting circuits, power consumption increases.

Therefore, the flip-flop circuit is not suitable as a memory cell for a large-capacity storage device that requires high integration and low power consumption.

Therefore, a method is known in which the load MISFET of the flip-flop circuit is removed as a memory cell of a large-capacity storage device, the gate capacitance of the drive MISFET is used, and the flip-flop is held by the charge stored in the gate capacitance.

This charge disappears due to leakage current if left for a long time, so it is necessary to periodically regenerate this charge. However, by eliminating the load transistor, the degree of integration can be improved, and the current consumption can be reduced by reducing the current consumption to the gate capacitor. Since only the charging current is used, power consumption is extremely low.

Therefore, the above-mentioned memory cell is suitable for mass storage devices, but on the other hand, it has the troublesome problem of charge regeneration as mentioned above.

In this respect, the flip-flop circuit using the inverting circuit described above does not lose its memory content over time;
It is easy to use because the memory contents are retained by constantly conducting one inverting circuit.

In order to reduce the power consumption of a flip-flop circuit with the above load resistance, it is possible to improve the resistance value of the load resistance by increasing the resistance value, but with the current semiconductor integrated circuit technology, the power consumption of this inversion circuit cannot be sufficiently reduced. I just couldn't get a high resistance.

Furthermore, even if a high resistance value could be obtained, the occupied area could not be reduced.

In this application, high integration is achieved based on the development of a method for forming a resistor element that has a high resistance value of 10 to 100 GΩ and can be made extremely small by introducing low concentration impurities by ion implantation into polycrystalline silicon. The present invention provides a flip-flop circuit having a low power consumption.

The configuration of the present invention for achieving the above object includes a cross-coupled circuit formed by cross-coupling the input terminal and output terminal of a pair of inverting circuits each comprising a load element and a drive MISFET connected in series; In a memory cell circuit device comprising a pair of transmission gate MISFETs coupled to the output terminals of the pair of inverting circuits, polycrystalline silicon having a high resistance value of about 10 to 1 OOGΩ is used as the pair of load elements. It is characterized by

The present invention will be specifically described below along with examples and with reference to the drawings.

FIG. 1 shows a memory cell circuit.

As shown in the figure, load resistances R1 and R2 and drive MISF
A memory cell circuit according to the present invention in which an input terminal and an output terminal of an inverting circuit in which ETM1 and M2 are connected in series are connected to each other, and transmission gates MISFET M3 and M4 are connected to the respective output terminals. As shown in FIG. 2, the load resistances R1 and R2 are
It utilizes a high resistance 4'' formed by introducing low concentration impurities into polycrystalline silicon by ion implantation.

The present invention will be explained in more detail below using an example of forming the high resistance 4''.

Polycrystalline silicon is formed by vapor phase chemical growth on the SiO2 film 2 and gate insulating film 2' formed on the surface of the semiconductor substrate 1, and when forming regions 3 such as sources and drains, Polycrystalline silicon and a portion of the polycrystalline silicon used for wiring, except for a portion forming high resistance, provide conductivity and form gate electrodes and wiring 4'.

Next, low concentration impurities are introduced into the polycrystalline silicon forming the high resistance by ion implantation to obtain a high resistance of 4''.

If the impurities are introduced at, for example, about 1012 to 1013-2 impurities/cm3, a resistance value of 10 to 100 GΩ can be obtained.

According to the present invention explained above, the object can be achieved for the following reasons.

Since the load resistance has a high resistance value of about 10 to 100 GΩ, the current flowing through one of the inverting circuits that is conducting is only a few points.
The power consumption is approximately A, resulting in extremely low power consumption.

Further, the resistor does not require a large occupied area and therefore can be highly integrated.

Therefore, it can be configured as a large capacity storage device.

In this case, since the flip-flop becomes a static flip-flop that does not require any rewriting or other operations, the peripheral control circuit becomes simple, and the peripheral circuit can be omitted as a result of the above, further improving the degree of integration.

That is, in the present invention, the leakage of the charge stored in the gate capacitance of a conventional memory cell such as the above-mentioned flip-flop circuit without the load MISFET is compensated for through a polycrystalline silicon resistor with a high resistance value, thereby increasing the information charge. Therefore, it is possible to obtain a static memory cell circuit device that does not require a peripheral rewrite circuit for memory retention as in the prior art.

Moreover, at this time, memory is retained through a polycrystalline silicon resistor with a high resistance value that compensates for the leakage charge.
The current consumption required for memory retention is reduced by the load MISFET mentioned above.
It is possible to make the memory cell circuit device much smaller by an order of magnitude compared to the memory cell circuit device using the memory cell circuit device, and it is possible to obtain the effect that the respective problems in both of the above-mentioned conventional memory cell circuit devices can be solved simultaneously.

The present invention is not limited to the above-mentioned embodiments, but can take various embodiments.

Any method of manufacturing the load resistor may be used as long as a high resistance is obtained by introducing low concentration impurities into polycrystalline silicon by ion implantation.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a memory cell circuit, and FIG. 2 is a sectional view of a load resistor according to the present invention. 1...Substrate, 2,2'...SiO2 film, 3...Source/drain, 4...Gate, 4'... Wiring, 4″...Load resistance, 5...Electrode, M1-M4...MI
SFET, R1-R2...Load resistance.

Claims (1)

[Claims] 1. A pair of driving MISFETs cross-coupled to each other;
a transmission gate MISFET connected to the output terminal of the pair of drive MISFETs, and a transmission gate MISFET connected to the output terminal of the pair of drive MISFETs;
A memory cell circuit device comprising polycrystalline silicon resistors each having a high resistance value of about 10 to 100 GΩ and connected between an output terminal of an SFET and a power supply terminal. 2. The memory cell circuit device according to claim 1, wherein the high resistance value of the polycrystalline silicon resistor is obtained by introducing impurities by ion implantation.