JPS6030107B2 - MIS type semiconductor memory device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an MIS type semiconductor memory device.

As an MIS type semiconductor memory device, there is one in which a memory cell is formed by a flip-flop formed by connecting two inverters each consisting of a load MISFET and a driving MISFET in a fixed manner. This is called a static type memory for comparison with a dynamic type memory which will be described later. Incidentally, it is necessary to reduce the power consumption of a semiconductor memory device as much as possible, and for this purpose, it is necessary to reduce the power consumption of the memory cells that constitute the memory device.

For this purpose, it is necessary to reduce the channel conductivity 8 (channel width W/channel length 1) in the load MISFET, and as a result, the channel length 1 has to be increased. Therefore, M for load
A problem arises in that the size of the ISFET increases and the integration density deteriorates. Of course, dynamic memory type semiconductor storage devices do not consume unnecessary power and the size of the memory cells can be small, but since the stored information is lost due to leakage current, refreshing is required and complex circuit operation is required. Therefore, it does not essentially solve the above problem because it requires a complicated peripheral circuit.

Therefore, it is an object of the present invention to reduce power consumption in a static memory without increasing the area occupied by the semiconductor memory device.

To achieve the above object, the present invention includes a pair of inverters each having one end of a pair of load elements electrically connected to the drains of a pair of drive MISFETs, and a gate of the drive MISFET of one of the inverters. and a flip-flop configured by electrically connecting the drain to the drain and gate of the driving MISFET of the other inverter, and the drain of the driving MISFET of the pair of inverters and the pair of digit lines. A pair of transmission MISFETs whose sources and drains are electrically connected to each other and whose gates are electrically connected commonly to the word line; a first wiring for electrically commonly connecting the other ends; and a second wiring for electrically commonly connecting the sources of the pair of drive MISFETs to a reference potential. In a MIS type semiconductor memory device comprising a memory cell on a semiconductor substrate, the first wiring and the load element are integrally formed by a polycrystalline silicon layer formed on the semiconductor substrate with an insulating film interposed therebetween. It is characterized by:

The present invention will be explained below with reference to Examples.

All drawings relate to one embodiment of the invention.

FIG. 1 is a layout diagram of a memory cell.

Portion 1 indicated by a dashed-dotted line is a diffusion layer formed by selectively diffusing impurities of a conductivity type opposite to that of the substrate on the surface of the semiconductor substrate.
Portions 2a, 2b, 2c indicated by broken lines are polycrystalline silicon layers, 2a is a power supply line (VooLine), 2b is one end of transmission FETs Q3, Q4, the drain of drive FETs Q, Q2, and drive FETs Q2, Q, The line 2c connecting the gate of R and the load resistance R, , R2 is the word line (
WordLine). 3a and 3b are load resistors R
,,3a in the polycrystalline silicon layer constituting R2 is R2,3
b is R.

This is formed integrally with the polycrystalline silicon layers 2a and 2b, but has a lower impurity concentration and a higher specific resistance than the polycrystalline silicon layers 2a and 2b. Portion 4 indicated by a thin solid line is the load resistor R.
, CVD-Si02 film covering the R2 part, parts 5a, 5b, 5c shown by thick solid lines are aluminum electrode wiring films;
a is the true digit line (dLi ship), 5b is the ground line (GNDLine), and 5c is the bird digit line (dLine). 6a and 6b are transmission FEs
The contact parts between the diffusion layer and the electrode wiring part that constitute the end portions of TQ and Q4, and the parts 7b and 7a indicated by two-dot chain lines, are the drive FETQ, the silicon gate of Q2 and the transmission FETQ.
, Q3 is a contact portion with a diffusion layer that constitutes one end portion of Q3.

FIG. 2 is a wiring diagram of this memory cell.

FIG. 3 is a cross-sectional view of the semiconductor device showing the MISFET and the load polycrystalline silicon layer section.

1 is a diffusion layer, 8a is Si0 for semiconductor surface passivation.
2 film, 8b is a gate insulating film; 0 is a semiconductor substrate.

Further, 2a, 2b, 2c are low resistance polycrystalline silicon layers,
3a is a high resistance polycrystalline silicon layer constituting a load resistance. As described above, according to the present invention, firstly, the load means of the inverter constituting the flip-flop is constructed of a polycrystalline silicon layer with a low impurity concentration or a high resistivity containing no impurities, so that the area occupied by the load means is reduced. It is possible to reduce the resistance value, increase the resistance value, and reduce the area occupied by the memory cell.

Second, since the polycrystalline silicon layer constituting the load means and the polycrystalline silicon layer for applying the power supply voltage VoD to the load means can be integrally formed, a special This eliminates the need for a contact area, and the area occupied by the contact area can be reduced. Furthermore, in order to retain the stored information, how much current should be supplied through the load means is shown in Figure 4 (for a room temperature of 2500 m) and Figure 5 (for a room temperature of 7000 m2).
).

This shows a correlation diagram between the holding current and the applied voltage V skin in two cells for four samples a, b, c, and d. As is clear from this figure, when the room temperature is 25 oo,
Even in sample a, which requires the largest holding current, when the power supply voltage Voo is 12V, the current is about 5×10 −6 A per memory cell, which makes it possible to hold information.

Therefore, the power consumption per memory cell is 0.6×1
06W (0.6rW) is sufficient. Note that as the temperature of the device increases, the current required to retain information increases.

This is because the current leaking through the junction increases as the temperature rises. FIG. 5 shows the required holding currents for the same samples a, b, c, and d as in FIG. 4, and the above-mentioned fact becomes clear when these two figures are compared. By the way, leakage current increases with temperature rise, but according to the present invention, the specific resistance of the polycrystalline silicon layer used as the load means decreases with temperature rise, so the supply current increases with the increase in leakage current. There is no fear that information retention will become impossible due to temperature rise.

Note that the resistance of the portion of the polycrystalline silicon layer constituting the load means is controlled by adjusting the amount of impurity implanted, for example, by ion implantation.

FIG. 6 is a correlation diagram showing the correlation between the ion implantation amount and the resistance value Ro. When the amount of ion implantation is less than 1 to 5 per cent, the resistance value is approximately constant at 1 to 5 per cent, making it easy to control the resistance value. However, it goes without saying that when the holding current is large, it is necessary to increase the amount of ion implantation in order to lower the resistance value. The present invention can be widely applied to static MIS type semiconductor memory devices. The film for covering parts 3a and 3b is CVD-
It is not limited to the Sj02 film, but may also be an insulating film such as a Si3N4 film.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a memory cell according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the memory cell, and FIG. 3 is a MISF
A cross-sectional view showing the ET section and the load resistance section, Figures 4 and 5 are correlation diagrams between the current required to retain information and the voltage used in the memory cell, and Figure 6 shows the amount of impurity implanted into polycrystalline silicon. It is a correlation diagram with resistance. 1... Diffusion layer, 2a, b, c... Polycrystalline silicon layer, 3a, b... Polycrystalline silicon layer constituting a load resistor, 4... ...CVD-Si02 covering the portion of the polycrystalline silicon layer that constitutes the load resistance
Films, 5a, b, c... Aluminum electrode wiring film, 6
a, b...Contact portion between the diffusion layer and electrode wiring, 7a, b...Contact portion between the polycrystalline silicon layer and the diffusion layer, 8a, b...Si02 film, 9... ...Semiconductor substrate, Q...MISFET, R...Resistance,
d, d... Nata line, V. . ...Power supply voltage, Word...Word line. False/Figure Z Figure Tsutomu 4 Figure younger brother Uzu Zutsu Figure inferior figure

Claims (1)

[Claims] 1 One end of a pair of load elements is connected to a pair of driving MISFETs.
a pair of inverters electrically connected to the drains of the driving MISFE of one of the inverters;
T and drain of the other inverter's driving MI
A flip-flop configured by electrically connecting the drain and gate of an SFET, and a source-drain path between the drain of the MISFET for driving the pair of inverters and the pair of digit lines, respectively. a pair of transmission MISs that are electrically connected to each other and whose gates are electrically commonly connected to the word line.
FET and a first terminal for electrically connecting the other ends of the pair of load elements in common in order to supply voltage to the other ends of the pair of load elements.
and a second wiring for electrically connecting the sources of the pair of driving MISFETs to a reference potential in order to connect the sources to a reference potential. A MIS type semiconductor memory device, wherein the first wiring and the load element are integrally formed by a polycrystalline silicon layer formed on the semiconductor substrate with an insulating film interposed therebetween. . 2. Each of the load elements consists of a region in which impurities are introduced by ion implantation into a selected portion of the polycrystalline silicon layer, and the region has a higher specific resistance than other portions of the polycrystalline silicon layer. An MIS type semiconductor memory device according to claim 1, characterized in that it has: 3. Each of the load elements comprises a substantially impurity-free region in the polycrystalline silicon layer, and the region has a higher resistivity than other parts of the polycrystalline silicon layer. MI according to claim 1
S-type semiconductor memory device.