JPS5845734B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration of an image processing apparatus, which is particularly characterized by the method of using a storage device.

Conventionally, when processing television images using a computer, the image information is temporarily stored and processed, so the processed image information is read out from the computer's own internal memory and then from this memory. An external memory dedicated to the picture frame was used to output continuous television video signals.

However, these memories have virtually the same configuration and store almost the same data, making them wasteful and requiring complicated software.

The present invention uses a single shared memory as the internal memory of the central processing unit for image processing and also as the memory for reading image information, thereby omitting part of the memory compared to conventional devices. The purpose of this invention is to provide a device that can simplify and speed up software.

Furthermore, the present invention provides an apparatus suitable for processing zero-period video at a television station by driving a combination coater and its peripheral equipment based on a television synchronization signal synchronized with a television synchronization signal. purpose.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

In this figure, the output of an A/D converter 1 that converts an image data signal, which is an analog signal, into a digital signal, and position information that determines the position of the image data signal on a television screen are input to an input terminal of an input device 2. Connected to give.

The input device 2 is an interface for a central processing unit (hereinafter referred to as CPU) 3.

The CPU 3 is an arithmetic unit that performs image processing of input data if necessary. For example, the CPU 3 has a capacity of 32 bytes.
It is connected to the dedicated memory 4 of.

Further, a data switch 5 is connected to the CPU 3 for writing data into the shared memory 6 and reading the data in accordance with the operation thereof, and an address multiplexer 7 is connected to the CPU 3 for specifying the address of the shared memory 6 in a time-sharing manner. has been done.

In the following embodiment, a case will be described in which the CPU 3 uses the shared memory 6 for 1/4 of the total time.

One horizontal scanning line of a television image consists of, for example, 256 dot picture elements, and each dot has 4 bits, or 16
It will be displayed in stages of level, and 1 field will be 25
Assuming that it is composed of 6 horizontal scanning lines, the amount of information (bits) in the field is 256 x 4 x 256 = 32
X210 X 8 (bits).

That is, in order to store information for one field in the shared memory 6, a memory having a storage capacity of 32 bytes is required.

This shared memory 6 is transferred to the dedicated memory 4 at the timing of the CPU.
In order to use the memory in the same way as the CPU, it is necessary to use a memory that can withstand a cycle speed several times the cycle time of the CPU.

In addition, the shared memory 6 is connected to the CPU 3 via the data switch 5.
The read data output terminal is also connected to the scratch read register 11.

On the other hand, the television synchronization generation unit 10 that generates a television synchronization signal that can be synchronized with the synchronization signal of an external television is, for example, 10.
It also includes an oscillator that generates 7 MHz as a reference clock, the output of which is connected to a CPU clock frequency divider 8 and a sweep address generator 9.

The CPU clock frequency divider 8 is a divider that divides the reference clock of the 10.7 MHz TV synchronization signal generated by the TV synchronization generator 10 into, for example, 1/3, and its output is connected to the CPU 3. .

The sweep address generating section 9 divides the reference clock generated by the television synchronization generating section 10 into 1/3, and divides it into approximately 3-58.
MHz and a minuter to count this signal 215
It includes a forward counter and a circuit for inhibiting counting of every fourth pulse of the counter's power,
The outputs of each of the 15 flip-flops constituting this 215-decimal counter are connected to an address multiplexer 7 as a sweep address signal for sequentially specifying addresses in the shared memory 6.

The scratch read register 11, which has the data output terminal of the shared memory 6 connected to its input terminal, includes six 4-bit registers and a frequency dividing unit that divides the reference clock signal of the TV synchronization signal of the TV synchronization generator 10 into 1/4. The data input to these registers is performed at the timing of the shared memory 6, which is 1/3 of the reference clock, while the data output from these registers (1/4 of the J reference clock). The shared memory 6 is used by the CPU.
It has a function that allows it to continuously output television images even while the device is being used.

The output of this scratch read register 11 is connected to a D/converter 12 to become an analog signal, and is further connected to a synchronization adder 13 to provide a television composite synchronization signal 710.

Next, the operation of this embodiment will be explained with reference to the waveform diagram shown in FIG.

In this figure, A is approximately 10.7 of the TV synchronization generator 10.
It represents a reference clock signal with a wave number of MHzfff, and the figure shows the CP signal obtained by dividing the reference clock into 1/3.
This is the approximately 3.58 MHz output signal of the U clock frequency divider 8.

Furthermore, C and C of the same figure are signals for controlling the address multiplexer 7, which are divided into 1/4 and have a duty time ratio of 25 to 75, respectively.

As described above, image data signals and position information are applied to the CPU 3 via the input device 2 and processed by a processing program stored in the dedicated memory 4.

Here, the CPU time in Figure 2 C is the CPU time for the shared memory 6.
This is the time for operating the memory as No. 3 memory.

A 16-bit signal is required to specify the address of the shared memory 6, and the 16-bit address signal of the CPU 3 specifies the address of the shared memory 6 via the address multiplexer 7 during the CP and U times.

Therefore, reading or writing by the CPU 3 is limited to the CPU time as shown in FIG.

On the other hand, within the sweep successive time shown in FIG. 2C, which has the opposite polarity to the CPU time in FIG. sent to.

In this case, the 215-decimal counter operates and counts up at the moment when each period of RO, R1, and R2 shown in FIG. 2 starts, and does not count up at the moment when the CPU time starts as described above.

In this manner, data at consecutive addresses in the shared memory 6 is read during the sweep read time, and read is prohibited during the CPU time and read intermittently.

This intermittent data is simply stored in the six 4-bit registers of the scratch read register 11 as described above, and the signals of each register are sequentially changed to 4 bits for each register as shown in Figure 2. Read out.

This readout interval is here 186ns (-279n
s×4÷6), and these four bits correspond to one dot mentioned above.

In this way, the intermittent data read from the shared memory 6 within the shortened sweep read time becomes continuous data for each dot that is restored to normal time by the scratch read register 11, and is then transferred to the D/A. The signal is transferred to the converter 12.

- Since the horizontal scanning line consists of 256 dots, the time required for this is 128 ns x 256 #47 μs,
A television composite synchronization signal is added to this analog signal output by a synchronization addition 13 to produce a video signal output.

In addition, FIG. 2 is a waveform diagram showing a clock signal obtained by further dividing the output port of the CPU clock frequency divider 8 into 174 within the CPU 3.

In a synchronous bus type CPU, the CPU for shared memory 6
In order to completely eliminate waiting time, it is necessary to use it as a clock signal synchronized with the television synchronization signal.

This does not apply to CPUs other than synchronous bus type.

As described above, according to the configuration of the present invention, the processed image can be processed by simply storing the data processed in the CPU in the shared memory, without using a method such as writing to the image-dedicated memory via an input device or direct memory access. can be displayed on the TV screen.

Therefore, a television style graphic display,
It is possible to simplify and speed up software when performing pattern recognition and other image processing.

Furthermore, there are storage devices such as Guinami Miku memory that require constant refreshing, but when using this type of memory, it can be refreshed by television sweep, so a dedicated refresh circuit is not required.

Furthermore, as described above, since the apparatus of the present invention is configured to operate all the peripheral devices such as the scratch read register 11 of the CPU and the sweep address generation section based on the above-mentioned television synchronization signal, the synchronized video at the television station is It is extremely suitable for processing.

In this embodiment, the sweep readout time and the CPU time are time-divided at a ratio of 3=1, but it goes without saying that this ratio can be freely selected depending on the conditions of use.

Furthermore, although this embodiment has shown a configuration in which image data is input to the shared memory only via the CPU, it is also possible to configure the image data to be input to the shared memory in a time-sharing manner.

Furthermore, since this device can read and write image information at high speed in CPU time, it can also be used as a digital scan converter, and its application to ground movement display and various image processing can be considered.

Although the above-described embodiments are intended for black-and-white television imaging processing such as ultrasonic images, processing of color images can be similarly performed by increasing the sampling wave number.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a waveform diagram showing waveforms of each part of the present invention with time axes aligned. 1... A/D converter, 2... Input device, 3... C
P.U. 4... Dedicated memory, 5... Data switch, 6...
Shared memory, 7...Address multiplexer, 8...
・CPU clock frequency divider, 9...Sweep address generation section, 10 TV synchronization generation section, 11...Scratch read register, 12...D/A converter, 13...Synchronization power port .

Claims (1)

[Claims] 1. A reference frequency generator that oscillates a TV synchronization signal synchronized with the TV synchronization signal, a memory circuit that stores one field of digitized image data, and an input circuit that operates based on the TV synchronization signal. a central processing unit that processes digitized data from the unit or image data stored in the memory using a program in another memory and writes the image data to a designated address in the memory; and a central processing unit that operates based on the television synchronization signal. a sweep address generator that sequentially and intermittently specifies addresses in the memory with intermittent rest periods occurring at intervals based on the frequency division output by counting the division output of the reference frequency generator; and the central processing unit. The address specified by the reference wave number generator and the sweep address of the sweep address generator are switched by time division based on the minute output of the reference quantity wave number generator, and the switching is performed during the pause period of the sweep address by the central processing unit. an address multiplexer that specifies the address of the memory; and an address multiplexer that specifies the address of the memory, reads and stores the data in the memory corresponding to the address specified by the sweep address, and stores the data in the memory based on the television synchronization signal. An image processing apparatus comprising: a scratch read register that continuously retrieves data of the image processing apparatus.