JPH0450612B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to characters generated under the control of a CPU, etc.
This invention relates to an image display device that outputs information such as graphic figures to a display device such as a CRT.

[Conventional technology]

As a conventional image display device of this kind, there is one described, for example, in the document "Microprocessor Peripheral LSI" (Nikkei McGraw-Hill), pages 183 to 236.

FIG. 4 shows a block diagram of the image display device. In the figure, 1 is a control unit such as a CPU, 2 is an image memory, 3 is a display address generator, and 4 is a parallel output from the image memory 2. A parallel/serial conversion unit converts data into serial data, and numerals 5 and 6 are bus arbiters for a data bus and an address bus.

Next, the operation will be explained. First, the data displayed on the display screen is passed through the bus arbiter 5.
It is written into the image memory 2 by a control unit 1 such as a CPU. Then, for example, the image is read out from the image memory 2 in accordance with the address of the display address generation section 3 which generates addresses at necessary timings for a display device such as a CRT. Therefore, the image memory 2 will be accessed by both the control unit 1 such as the CPU and the display address generation section 3. To prevent bus collisions, bus arbiters 5 and 6 are provided. Tracing is performed.

Control unit 1 such as CRU to image memory 2,
Alternatively, access from the display address generation unit 3 is performed by time division, which generally involves two
There are different methods. The following explanation will be continued using CRT as an example of a display device. In this case, due to the scanning method of the electron beam, there is a period in which well-known data is displayed on the CRT screen (hereinafter referred to as the display period) and a period in which it is not displayed (hereinafter referred to as the blanking period).
exists. In order to maintain stable display on the CRT screen, it is necessary to continue outputting data to the CRT during the display period. The easiest way to do this is to prohibit the control unit 1 such as the CPU from accessing the image memory 2 during the display period, and to prohibit the control unit 1 such as the CPU from accessing the image memory 2 only during the blanking period.
This is a method that allows access to the image memory 2.
Another method is to increase the number of pixels corresponding to the display data that is read out from the image memory 2 to the parallel-to-serial converter at one time, thereby reducing the surplus period for the display address generator 3.
This is a method in which a control unit 1 such as a CPU allocates access times to the image memory 2. Normally, the display data stored in the image memory 2 pixel by pixel is
Due to the access time of the memory IC used in image memory 2, several pixels are read out at once.
The parallel-to-serial converter 4 in the next stage separates the data into display data for one pixel, and sequentially outputs the data to a display device. In this case, the display data read out from the image memory 2 at a time corresponds to the value obtained by dividing the time corresponding to the display period within one horizontal scanning period by the access time of the memory IC used in the image memory 2. It is most efficient in terms of time to match the number of pixels. On the other hand, if the number of pixels corresponding to the display data read out from the image memory 2 at one time without changing the access cycle to the memory IC is larger than the value obtained above, for example twice, then one display The time required to read out all the display data required for a period from the image memory 2 is only 1/2 the time required for that display period. In other words, if you double the amount of data handled in one access, the number of accesses required will be halved. This surplus time or access timing is handed over to the control unit 1.

[Problems to be Solved by the Invention] Since the conventional image display device is configured as described above, in the case of the first method, the display period out of the time required to configure one display screen is For other periods, for example, in the case of CRT, it is only 20-30%,
If an attempt was made to rewrite all the data for one display screen using only this period, there was a problem in that it would take a lot of time. In addition, in the case of the second method, the increase in the number of data handled at once means the number of parts, especially the memory that constitutes the image memory 2.
There were problems such as an increase in the number of ICs and a high cost.

This invention was made to solve the above-mentioned problems, and the memory used for the image memory 2
An object of the present invention is to provide an image display device that reduces the time required for a control unit such as a CPU to write data for one display screen into an image memory without increasing the number of ICs.

[Means for solving problems]

An image display device according to the present invention includes an image memory that stores data displayed on a display screen in units of pixels, a control unit such as a CPU that performs writing processing of the data to the image memory, and the image memory. A buffer memory located between the control unit and the control unit is provided, and the control unit such as the CPU writes data to be displayed on the display screen into the image memory via the buffer memory.

[Effect]

In the image display device according to the present invention, a control unit such as a CPU performs writing processing on the buffer memory during the display period when the image memory is outputting display data to the display device, and transfers data from the buffer memory to the image memory. is performed during a period when the image memory does not need to output display data to the display device, for example, in the blanking period for a CRT.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 4 are designated by the same reference numerals. In FIG. 1, 7 is a buffer memory section. FIG. 2 is an internal block diagram of the buffer memory unit 7 shown in FIG. 1. Reference numerals 11 and 12 are buffer memories, 13 is a buffer memory address generation unit that generates addresses for writing and reading from the buffer memory, and 14 is a read/write address for the buffer memory. This is a control signal generating section that generates a write switching signal, a write pulse to the image memory, etc.

Next, the operation will be explained. Here, the display device is a CRT. First, during the display period, the buffer memories 11 and 12 in FIG.
is connected to a control unit 1 such as a CPU, and the data to be displayed on the display screen generated by the control unit 1 and the address on the image memory 2 where the display data is to be stored are transmitted to the control unit 1 such as the CPU. The data is written into the buffer memories 11 and 12 by the write pulse generated. In this case, the control unit 1 such as the CPU does not need to be particularly aware that the buffer memories 11 and 12 are the objects to which display data is written. This is because the write addresses for the buffer memories 11 and 12 are generated not by the control unit 1 such as the CPU but by the buffer memory address generation section 13. Next, during the retrace period, the buffer memory 1
1 and 12 are connected to the image memory 2, and the buffer memories 11 and 12 are connected to the image memory 2 by the control unit 1 during the display period.
The display data written in 12 and the address on the image memory 2 where the display data is stored are read out from the buffer memories 11 and 12 according to the address generated by the buffer memory address generation section 13, and the control signal generation section 14 is supplied to the image memory 2 together with the generated light pulse, and display data is written into the image memory 2.
The time required for data transfer in this case is determined by the access time of the memory ICs used in the image memory 2 and buffer memories 11 and 12. However, it takes about a fraction of the time it takes for the control unit 1 such as the CPU to perform the data writing process, and even if the period for writing display data to the image memory 2 is limited to within the retrace period, A sufficient amount of display data can be written into the image memory 2.

Next, the buffer memory address generation section 13 will be explained. Buffer memory address generation section 13
The up-down counter is mainly composed of an up-down counter, and when writing is performed from the control unit 1 such as the CPU to the buffer memories 11 and 12, the up-counter counts the write pulses output by the control unit 1 such as the CPU, and the buffer memories 11 and 12 12 to the image memory 2, a down counter counts clock pulses generated by the control signal generator 14 to generate addresses for the buffer memories 11 and 12. FIG. 3 shows a time chart of the buffer memory address generation section 13. here,
First, when writing to the buffer memories 11 and 12 is permitted from the control unit 1 such as the CPU, the value of the counter holds zero. In this state, when the control unit 1 such as the CPU starts writing to the buffer memories 11 and 12, the write pulses output from the control unit 1 such as the CPU are counted, and if N+1 write pulses are output, the value of the counter is Proceed to N+1. However, the final value N+1 is buffer memory 11, 12.
It is not added to writing to . That is, the display data output from the control unit 1 such as the CPU and the address on the image memory 2 where the data is to be stored are stored at addresses 0 to N of the buffer memory. Here, when writing from the control unit 1 such as the CPU to the buffer memories 11 and 12 is prohibited and transfer of display data from the buffer memories 11 and 12 to the image memory 2 is permitted, the counter is activated by the clock pulse output from the control signal generator 14. Starting with countdown, counting is prohibited when the counter value reaches zero, and then
Buffer memory 11 of control unit 1 such as CPU,
It holds zero until write processing to 12 is permitted. That is, the buffer memories 11 and 12
The display data stored from address 0 to address N of the image memory 2 where the data should be stored.
The address above is read. As above
A control unit 1 such as a CPU has a buffer memory 11,
Buffer memory 1 without being particularly conscious of 12
1 and 12, display data can be written to the image memory 2.

Note that the timing chart shown in FIG. 3 is only an example, and the timing chart is not limited thereto.

〔Effect of the invention〕

As described above, according to the present invention, a buffer memory section is provided between a control unit such as a CPU and an image memory, and the control unit such as a CPU writes display data to the image memory via the buffer memory section. This has the effect that display data for one display screen can be written into the image memory at sufficient speed without increasing the number of parts, especially the number of memory ICs used in the image memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is an internal block diagram of the buffer memory section in FIG. 1, and FIG. 3 shows the operation of the buffer memory address generation section in FIG. The time chart to be explained in FIG. 4 is a block diagram of a conventional image display device. In the figure, 1 is a control unit such as a CPU, 2 is an image memory, 3 is a display address generation section, 7 is a buffer memory section, 11 and 12 are buffer memories, 13
is a buffer memory address generation section.

Claims (1)

[Scope of Claims] 1. An image display device that outputs display data generated by a control unit and output to a display screen from an image memory storing pixel units to a display device, wherein the control unit and the image memory A buffer memory section is provided between the two, and the buffer memory section stores display data outputted by the control unit during the display period for the display device, and counts up write pulses given to the buffer memory by the control unit. a buffer memory address generating section which supplies a count value to the buffer memory as a write address and down-counts a clock pulse and supplies the count value to the buffer memory as a read address; An image display device comprising: a control signal generating section that outputs a clock pulse and also supplies a write pulse to the image memory. 2. The image display device according to claim 1, wherein the buffer memory section stores data to be displayed on the display screen output from the control unit and an address on the image memory to store this data.