JPS5846063B2 - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a vertical field effect transistor and a lateral bipolar transistor are formed, and an improvement in a manufacturing method thereof.

Conventionally, as a semiconductor device in which a vertical field effect transistor and a lateral bipolar transistor are formed, the first
The configuration shown in the figure has been proposed.

That is, it has a semiconductor substrate 3 consisting of, for example, an N-type semiconductor layer 1 having a relatively high impurity concentration, and an N-type semiconductor layer 2 having a relatively low impurity concentration disposed on the semiconductor layer 1.

Therefore, an N-type semiconductor region 4 having a relatively high impurity concentration is formed in the semiconductor layer 2 of the semiconductor substrate 3 from the upper surface side.
A P-type semiconductor region 5 that is connected to and surrounds the semiconductor region 4, and a P-type semiconductor region 6 outside the semiconductor region 5 are formed.

Further, electrodes 7, 8 and 9 are attached to the semiconductor regions 4, 5 and 6 from above, respectively.

Note that 10 is an insulating layer extending over the semiconductor layer 2.

The above is the configuration of a conventionally proposed semiconductor device.

In a semiconductor device having such a configuration, the semiconductor layer 1 is a drain, the semiconductor region 4 is a source, the semiconductor region 5 is a gate, the region of the semiconductor layer 2 below the semiconductor region 4 is a channel, and the electrodes 7 and 8 are electrodes for source, respectively. and a junction type vertical field effect transistor in which semiconductor regions 5 and 6 are used as collector and emitter regions, respectively, and the region between semiconductor regions 5 and 6 of semiconductor layer 2 is used as a base, and electrodes 8 and 9 are used as collector electrodes, respectively. and a lateral bipolar transistor serving as an emitter electrode.

In this case, the collector of the lateral bipolar transistor is internally connected to the gate of the vertical field effect transistor, and the base of the lateral bipolar transistor is internally connected to the drain of the vertical field effect transistor.

Therefore, by applying an input between the semiconductor layer 1 and the electrode 9, a unit logic circuit is constructed in which an output can be obtained between the semiconductor layer 1 and the electrode 7.

However, in the case of the conventional semiconductor device shown in FIG. (Semiconductor area 5)
Although it is desired that the junction capacitance between the semiconductor layer 1 and the drain (semiconductor layer 1) be sufficiently small, it is particularly important that the gate (semiconductor region 5) is formed in the semiconductor layer 2 with a small size. Therefore, they had the disadvantage that their junction capacitance could not be sufficiently reduced.

Therefore, the present invention aims to propose a novel semiconductor device and its manufacturing method free from the above-mentioned drawbacks, as will become clear from the following description. The semiconductor device according to the invention and its manufacturing method will be described using an example of the manufacturing method.

In an example of the method for manufacturing a semiconductor device according to the present invention, the second
As shown in FIG. A, an N-type semiconductor layer 11 made of, for example, an N-type silicon substrate and having a relatively high impurity concentration;
Thereon, a silicon semiconductor substrate 13 is prepared in advance, including an N-type semiconductor layer 12 formed by, for example, epitaxial growth and made of N-type silicon and having a relatively low impurity concentration.

Thus, a first oxide layer (not shown) and a first nitride layer (not shown) are formed on the semiconductor layer 12 of the semiconductor substrate 13.
and, in that order, by methods known per se,
The first nitride layer is then selectively etched to form a nitride layer 14, a nitride layer 15 surrounding the nitride layer 14, and a nitride layer 15 surrounding the nitride layer 14, as shown in FIG. 2B. The nitride layer 16 on the outside of the nitride layer 15 is formed as second, third, and fourth nitride layers, respectively.

Next, using the nitride layers 14.15 and 16 as a mask, the first oxide layer is over-etched to etch the oxide layers 17.18 contained in the nitride layers 14.15 and 16, respectively, as seen from above. and 19 as the second, third and fourth oxide layers, respectively.

Next, nitride layers 14, 15 and 16 and oxide layers 17.
18 and 19 as a mask, the semiconductor layer 12 is subjected to an anisotropic etching process to surround a partial region of the semiconductor layer 12 from the upper surface side of the semiconductor layer 12, as shown in FIG. 2C. A groove 20 having an inverted triangular cross section extending toward the semiconductor layer 11 side, and a groove 20 extending toward the semiconductor layer 11 on the outside of the groove 20.
A groove 21 having an inverted triangular cross section extending from the upper surface side of the semiconductor layer 2 toward the semiconductor layer 11 side is formed as a first groove and a second groove, respectively.

Next, oxide layers 17, 18 and 19 and nitride layers 14.
A nitride film 22 is applied to the surfaces of grooves 15 and 16 facing the outside and the inner surfaces of grooves 20 and 21.

Next, using the nitride layers 14, 15 and 16 as a mask,
Ions of an inert element such as argon are implanted from above to form an ion implantation region 23 in the region of the nitride film 22 that is not in the shadow of the nitride layers 14, 15 and 16, as shown in the second diagram. and 24 are formed as the first ion implantation region.

Next, as shown in FIG.
by removing the inner lower part of each of the grooves 20 and 21,
The first exposed portion 26 is exposed.

Next, thermal oxidation treatment is performed to form an insulating layer 30 made of an oxide mainly containing silicon oxide as a first insulating layer on the exposed portion 26, as shown in FIG. 2F.

Next, the nitride film 22 and the nitride layers 14, 15 and 16 are removed, and as shown in FIG. 31, and then using the oxide layers 17, 18 and 19 as a mask, nitrogen ions are implanted from above to remove the regions of the exposed portion 31 that are not in the shadow of the oxide layers 17, 18 and 19. Next, the ion implantation region 32 is formed as a second ion implantation region.

Next, by thermal oxidation treatment, as shown in FIG.
3, an insulating layer 3 made of an oxide is placed on the ion implantation region 32.
4 are formed as second and third insulating layers, respectively.

Next, as shown in Figure 2, the insulating layer 34 is removed by etching to form third exposed portions 35 on the inner surfaces of each of the grooves 20 and 21.

Next, as described above, insulating layers 30 and 33 are provided on the inner surface,
In the grooves 20 and 21 forming the exposed portion 35, a second
As shown in FIG. J, polycrystalline semiconductor layers 40 and 41 made of, for example, polycrystalline silicon containing P-type impurities are grown and disposed by, for example, a growth method.

In this case, a polycrystalline semiconductor layer is also disposed on the oxide layers 17, 18 and 19, so that the polycrystalline semiconductor layer 40 and 4
1 are connected via polycrystalline semiconductor layers on oxide layers 17, 18 and 19.

Next, since the upper surfaces of the polycrystalline semiconductor layers 40 and 41 are recessed at the positions of the grooves 20 and 21, for example, a resist material is applied onto the polycrystalline semiconductor layers 40 and 41 so that the upper surfaces thereof are flat. The resist layer 42 is formed by coating the polycrystalline semiconductor layers 40 and 41 such that the polycrystalline semiconductor layers 40 and 41 are formed by implanting, for example, nitrogen ions into the resist layer 42 from above.
An ion implantation region 43 is formed on the non-concave region of the upper surface.

Next, the resist layer 42 is removed.

Next, by thermal oxidation treatment, polycrystalline semiconductor layers 40 and 4 are
1 and the ion implantation region 43 on the upper surface of the ion implantation region 4
An oxide film (not shown) is formed on each region where the ion implantation region 43 is not formed, and then the oxide film on the ion implantation region 43 is removed by etching the oxide films. As shown in FIG. 2K, the oxide film on the upper surfaces of the polycrystalline semiconductor layers 40 and 41 in the region where the ion implantation region 43 is not formed is left as an oxide film 44.

In this case, since heat treatment is performed, the groove 2 of the semiconductor layer 12
In the area surrounded by 0, the exposed portion 35 of the groove 20 is
The P contained therein is removed from the polycrystalline semiconductor 40 through the region surrounded by the trench 20 of the semiconductor layer 12.
A P-type semiconductor region 45 connected to the polycrystalline semiconductor layer 40 is formed by introducing the type impurity.

In addition, the polycrystalline semiconductor layer 40 is introduced into the region between the grooves 20 and 21 of the semiconductor layer 12 through the above-mentioned exposed portion 35 of the groove 20 on the side of the region between the grooves 20 and 21 of the semiconductor layer 12. The P-type impurity introduced into the semiconductor layer 1 forms a P-type semiconductor region 46 that is connected to the polycrystalline semiconductor layer 40, and the semiconductor layer 1 in the exposed portion 35 of the trench 21 is introduced.
The P-type impurity contained in the polycrystalline semiconductor layer 41 is introduced from the polycrystalline semiconductor layer 41 through the region between the grooves 20 and 21 in No. 2, forming a P-type semiconductor region 47 that is connected to the polycrystalline semiconductor layer 41. be done.

Next, by performing an etch lag process on the polycrystalline semiconductors 40 and 41 using the oxide film 44 as a mask, the polycrystalline semiconductor layers 40 and 41 are etched from the upper surface side to the oxide layers 17 and 18.
and 19, and thus the polycrystalline semiconductor layer 4
0 and 41 are made so that they are not connected to each other, then the oxide film 44 is removed by etching, and then thermal oxidation treatment is performed to remove the oxide layers 17 and 18 on the upper surfaces of the polycrystalline semiconductors 40 and 41. and 19, the second
As shown in the figure, an oxide film 48 connected to oxide layers 17 and 18 and an oxide film 49 connected to oxide layers 18 and 19 are formed.

In this case, since the heat treatment has been performed, the P-type impurity contained therein is introduced into the semiconductor regions 45 and 46 from the polycrystalline semiconductor layer 40, so that the P-type semiconductor region 45 becomes a semiconductor. Groove 20 of layer 12 (thus, P-type semiconductor region 45' extending into the enclosed area)
and a P-type semiconductor region 46' that extends into the region between the grooves 20 and 21 of the semiconductor layer 12; P-type semiconductor regions 47' extending within the region between the twelve trenches 20 and 21 are formed as second, third, and fourth semiconductor regions, respectively.

Next, a window is bored in the oxide layer 17 to expose the area surrounded by the groove 20 of the semiconductor layer 12 to the outside, and through the window, the area surrounded by the groove 20 of the semiconductor layer 12 is exposed to the outside.
N-type impurities are introduced from the upper surface side to form an N-type semiconductor region 50 having a relatively high impurity concentration as a first semiconductor region, as shown in FIG. 2M.

Note that, as shown in FIG.
A window (not shown) is made to expose the region between grooves 20 and 21 of the semiconductor layer 12 to the outside, and an N-type impurity is introduced into the region between the grooves 20 and 21 of the semiconductor layer 12 from the upper surface side through the window. An N-type semiconductor region 51 having a relatively high impurity concentration may be formed.

Next, windows are formed in the oxide films 48 and 49 to expose the polycrystalline semiconductor layers 40 and 41 to the outside, respectively, and the polycrystalline semiconductor layers 40 and 41 are inserted through the windows as shown in FIGS. Electrodes 52 and 53 are attached to 41, and electrode 54 is attached to semiconductor region 50 as well.

As described above, an example of the intended semiconductor device according to the present invention is manufactured.

As described above, an example of the semiconductor device and its manufacturing method according to the present invention has been clarified.

Such a semiconductor device according to the present invention (FIG. 2 M or N)
), the semiconductor layer 11 is the drain, the semiconductor region 50 is the source, the region under the semiconductor region 50 of the semiconductor layer 12 is the channel, the semiconductor region 45' is the gate, and the polycrystalline semiconductor layer 40 to the electrode 52 are the gates. a vertical field effect transistor in which the electrode 54 is used as a source electrode;
A lateral bipolar transistor is formed in which the semiconductor region 46' is the collector, the semiconductor region 47' is the emitter, and the region between the semiconductor regions 46' and 47' of the semiconductor layer 12 is the base.

In this case, the collector of the lateral bipolar transistor is internally connected to the gate of the vertical field effect transistor, and the base of the lateral bipolar transistor is internally connected to the drain of the vertical field effect transistor.

Therefore, the semiconductor device according to the present invention shown in FIG. It constitutes a unit logic circuit similar to that of the conventional semiconductor device.

However, in the case of the semiconductor device according to the present invention shown in FIG. 2M or N, the gate (
The semiconductor region 45') is formed in the groove 2 formed in the semiconductor layer 12.
Exposed portion 35 of groove 20 in polycrystalline semiconductor 40 arranged within 0
The source (semiconductor region 50 (
It has a configuration that is not connected.

Therefore, the junction capacitance between the source (semiconductor region 50) and gate (semiconductor region 45') of the vertical field effect transistor and the junction capacitance between the gate (semiconductor region 45') and drain (semiconductor layer 11) are expressed as follows: Even if the shape and size of the gate (semiconductor region 45') are the same as in the conventional semiconductor device described above in FIG. 1, compared to the conventional semiconductor device described in FIG. It can be significantly smaller.

Therefore, in the case of the semiconductor device according to the present invention shown in FIG. 2M or N, the vertical field effect transistor can be operated at a higher response speed than in the case of the conventional semiconductor device shown in FIG. Therefore, it has the feature that the functions of the unit logic circuit described above can be obtained with high response speed.

In addition, in the case of the semiconductor device according to the present invention shown in FIG. 2M or N, the distance between the gate (semiconductor region 45') and source (semiconductor region 50) of the vertical field effect transistor is
In the case of the conventional semiconductor device described above in FIG. 1, the area occupied by the gate and source on the semiconductor substrate 13 is reduced compared to the case of the conventional semiconductor device described above in FIG. can do.

This means that the emitter (
semiconductor region 47') and collector (semiconductor region 46')
? The same goes for getting stuck.

Therefore, in the case of the semiconductor device according to the present invention shown in FIG. 2M or N, compared to the case of the conventional semiconductor device described above in FIG. The present invention has a great feature that the withstand voltage of each of a type field effect transistor and a lateral bipolar transistor can be significantly improved compared to the case of the conventional semiconductor device described above with reference to FIG.

Further, according to the method for manufacturing a semiconductor device according to the present invention described above in FIGS. 2A to 2M or N, a semiconductor device having the above-mentioned excellent characteristics can be manufactured in a simple process. have

Note that in the case of the semiconductor device according to the present invention shown in FIG. 2N,
The semiconductor region 51 is formed in the region between the grooves 20 and 21 of the semiconductor layer 12, and an N-N+ junction is formed therebetween, and the N-N+ junction forms a potential barrier against holes. , the emitter efficiency of the lateral bipolar transistor is high, and therefore the function as a unit logic circuit can be effectively obtained.

Note that the above description is an example of a semiconductor device and a manufacturing method thereof in which a P-type semiconductor region connected to the polycrystalline semiconductor layer 41 is also formed in a region outside the groove 21 of the semiconductor layer 12. However, it is also possible to adopt a configuration in which the P-type semiconductor region connected to the polycrystalline semiconductor layer 41 is not formed in the region outside the groove 21 of the semiconductor layer 12.

In this case, you can do as follows.

In other words, the step shown in FIG. 2G after the steps described above in FIGS. and a step of forming an insulating layer 30 on the lower inner surface of each of the grooves 20 and 21, as shown in FIGS. 3A1 and 3A2.

Therefore, after taking the steps shown in FIG. 3 A1 and A2,
As shown in FIG. 3B, the groove 21 in the semiconductor layer 12
A resist layer 61 is applied on the side opposite to the area between and 21.

Next, as shown in FIG. 3C, nitrogen ions are implanted into the exposed portion 3 of the inner surface of the groove 21 in the same manner as described above in FIG. 2G.
1, an ion implantation region 32 is formed in the exposed portion 31 of the inner surface of each of the trenches 20 and 21, except for the side opposite to the region between the trenches 20 and 21 of the semiconductor layer 12.

Next, after removing the resist layer 61, as shown in the third diagram, the grooves 20 and 21 are thermally oxidized in the same manner as described above in FIGS. An insulating layer 33 and an exposed portion 35 are formed on the inner surface of each groove 2.
The semiconductor layer 12 on the inner surface of the groove 21 is formed except for the side opposite to the region between the grooves 20 and 21.
On the side opposite to the region between the grooves 20 and 21 of No. 2, only the insulating layer 33 is formed without forming the exposed portion 35.

Hereinafter, the same steps as those described above with reference to FIG. 2 J-M are performed.

Therefore, as shown in FIG.
Obtain a configuration that is not formed in the area outside of 1.

Further, in the above description, only a few examples of the semiconductor device and its manufacturing method according to the present invention have been shown.
The N-type described above can also be replaced with P-type.

Various other modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional semiconductor device. FIG. 2 is a line cross-sectional view of sequential steps showing an example of a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a cross-sectional view showing sequential steps showing another example of the method for manufacturing a semiconductor device according to the present invention. 11.12... Semiconductor layer, 13... Silicon semiconductor substrate, 14, 15, 16... Nitride layer, 17°18.19... Oxidation material layer, 20,
21...Groove, 22...Nitride film, 23,
24...Ion implantation region, 26...Exposed portion, 30...Insulating layer, 31...Exposed portion, 32...Ion Driving area, 33, 34...
...Insulating layer, 35...Exposed part, 40, 41
...Polycrystalline semiconductor layer, 42...Resist material, 43...Ion implantation region, 44...
...Oxide film, 45, 45', 46.46'47.47'
... Semiconductor region, 48, 49, oxide film, 50.
51...Semiconductor region, 52, 53°54...
. . . Electrode, 61 . . . Resist layer.

Claims (1)

[Claims] 1. A first semiconductor of a first conductivity type having a relatively high impurity concentration.
and a second semiconductor layer of a first conductivity type having a relatively low impurity concentration disposed on the first semiconductor layer; , a first groove having an inverted triangular cross section extending from the upper surface side of the second semiconductor layer to the first semiconductor layer side so as to surround a partial region of the second semiconductor layer; A second groove having an inverted triangular cross section extending from the upper surface side of the second semiconductor layer toward the first semiconductor side is formed outside the first groove, and On the inner surface of each of the second grooves, a first insulating layer is formed in the lower part, a second insulating layer is formed in the upper part, and an exposed part is formed between the first and second insulating layers. First and second polycrystalline semiconductor layers containing impurities of a second conductivity type are respectively disposed in the groove No. 2, and the second semiconductor layer has a polycrystalline semiconductor layer surrounded by the first groove. In the region, a first semiconductor region of a first conductivity type having a relatively high impurity concentration is formed from the upper surface side of the region, and the first semiconductor region of the second semiconductor layer in the exposed portion of the first trench is formed. A second semiconductor region having a second conductivity type that is connected to the first polycrystalline semiconductor layer is formed through the region surrounded by the groove, and a second semiconductor region having a second conductivity type is formed between the first and second grooves. A second polycrystalline semiconductor layer that is connected to the first polycrystalline semiconductor layer within the region through the region side between the first and second trenches of the second semiconductor layer in the exposed portion of the first trench. A third semiconductor region having a conductivity type is formed, and the second polycrystalline semiconductor layer is formed through the exposed portion of the second groove on the side of the region between the first and second grooves of the second semiconductor layer. A fourth semiconductor region having a second conductivity type is formed and is connected to the semiconductor layer, and the first semiconductor layer is a drain (or source), the first semiconductor region is a source (or drain), and the first semiconductor region is a drain (or source). A vertical field effect transistor has a second semiconductor region as a gate, the first polycrystalline semiconductor layer as a gate electrode, a collector (or emitter) as the third semiconductor region, and an emitter (or emitter) as the third semiconductor region. or collector), the region between the first and second grooves of the second semiconductor layer as a base, and the first and second polycrystalline semiconductor layers as a collector (or emitter) electrode and an emitter (or collector), respectively. A special conductor device characterized in that a lateral bipolar transistor is formed as an electrode. 2. A first conductivity type having a relatively high impurity concentration.
and a second semiconductor layer of a first conductivity type having a relatively low impurity concentration on the first semiconductor layer. and a first nitride layer in that order, and then selectively etching the first nitride layer to form a second nitride layer and a first nitride layer. a surrounding third nitride layer;
a fourth nitride layer outside the third nitride layer, and then overetching the first oxide layer using the second, third, and fourth nitride layers as a mask. and forming second, third and fourth oxide layers respectively included in the second, third and fourth nitride layers, as viewed from above; a fourth oxide layer;
Using the second, third and fourth nitride layers as a mask,
The second semiconductor layer is subjected to an anisotropic etching process, so that the first semiconductor layer side is etched from the upper surface side of the second semiconductor layer so as to surround a partial region of the second semiconductor layer. a first groove with an inverted triangular cross section extending by O; and a cross section extending from the upper surface side of the second semiconductor layer toward the first semiconductor layer outside the first groove; forming a second trench having an inverted triangular shape, the second, third and fourth oxide layers;
A nitride film is applied to the surfaces facing the outside of the and fourth nitride layers and the inner surfaces of the first and second grooves, and then the second and fourth nitride layers are coated with a nitride film.
Using the third and fourth nitride layers as masks, inert element ions are implanted into regions of the nitride film that are not shadowed by the second, third, and fourth nitride layers. forming an ion implantation region; and removing the first ion implantation region by taking advantage of the fact that the first ion implantation region of the nitride film is more easily etched than other regions; A step of exposing the lower inner surfaces of each of the first and second grooves as a first exposed portion, and then performing thermal oxidation treatment to form a first insulating layer on the first exposed portion. , the nitride film, and the second, third, and fourth
The nitride layer of the first and second grooves is removed to expose the regions excluding the lower inner surfaces of each of the first and second grooves as a second exposed portion, and then the second, third and fourth grooves are exposed as a second exposed portion. By implanting nitrogen ions using the oxide layer as a mask, a second ion implantation region is formed in a region of the second exposed portion that is not shadowed by the second, third, and fourth oxide layers. forming a second insulating layer on a region other than the second ion implantation region of the second exposed portion of each of the first and second grooves; A third insulating layer is formed on each of the ion implantation regions by thermal oxidation, and then the third insulating layer is removed by etching to form a layer on the inner surface of each of the first and second grooves. a step of forming a third exposed portion; and a step of arranging first and second polycrystalline semiconductor layers containing impurities of a second conductivity type in the first and second trenches, respectively; In the region surrounded by the first trench of the second semiconductor layer, a third exposed portion of the first trench is located on the side of the region surrounded by the first trench of the second semiconductor layer. Introducing impurities of a second conductivity type from the first polycrystalline semiconductor layer to form a second semiconductor region of a second conductivity type connected to the first polycrystalline semiconductor layer. and in a region between the first and second grooves of the second semiconductor layer, the first and second grooves of the second semiconductor layer in the third exposed portion of the first groove are formed. introducing an impurity of a second conductivity type from the first polycrystalline semiconductor layer through the region between the grooves,
forming a third semiconductor region of a second conductivity type that is connected to the first polycrystalline semiconductor layer; from the second polycrystalline semiconductor layer through the region between the two grooves,
a second conductivity type impurity is introduced to form a second conductivity type fourth semiconductor region connected to the second polycrystalline semiconductor layer; A first conductivity type impurity is introduced into the region surrounded by the first groove from the upper surface side to form a first conductivity type first semiconductor region having a relatively high impurity concentration. the first semiconductor layer as a drain (or source),
A vertical field effect transistor having the first semiconductor region as a source (or drain), the second semiconductor region as a gate, and the first polycrystalline semiconductor layer as a gate electrode, and the third semiconductor region as a collector. (or emitter)
, the fourth semiconductor region is an emitter (or collector)
, the region between the first and second grooves of the second semiconductor layer is used as a base, and the first and second polycrystalline semiconductor layers are used as a collector (or emitter) electrode and an emitter (or collector) electrode, respectively. A method for manufacturing a semiconductor device, comprising manufacturing a semiconductor device in which a lateral bipolar transistor is formed.