JPS5846179B2 - Mask ROM manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing an MIS type mask ROM, and particularly to a method for manufacturing an MIS type mask ROM that can shorten the manufacturing steps.

As a means for writing information in an MIS type mask ROM, there is a method in which a source region is not formed for the MIS transistor that stores information in a memory cell formed by a plurality of MIS transistors, or a method in which a gate insulating film is not formed. Conventionally, methods of forming the memory element thickly have been used, but all of the above methods have the disadvantage that the information writing process is located in the first half of the memory element manufacturing process, resulting in a very long manufacturing process.

Therefore, recently, the formation of MIS transistors in the entire area of memory cells is completed in advance, and a semiconductor IC substrate with an insulating film formed on the memory cells is prepared, and MIS transistors are added to the insulating film according to the order. When forming electrode windows, only source and drain electrode windows are formed except for the drain electrode window of the MIS transistor in which information is to be written, and then source wiring and drain wiring are formed on the insulating film. At this time, the transistor to which the information is to be written is turned off, and the information is recorded.

) Next, a method is generally used in which a cover insulating film is formed on the cell to provide a ROM element, but in this method as well, the number of steps from writing information to completing the ROM element is 1 element manufacturing step. It took a total of 7 to 7, so it still wasn't a short enough turn.

The present invention provides a method for manufacturing an MIS type mask ROM that further reduces the manufacturing steps by moving the information writing process to a later process.

That is, in the method of manufacturing a mask ROM of the present invention, an insulating film is formed on a substrate to be processed having a semiconductor layer on which a plurality of MIS transistors are formed, and then the MIS transistors are formed on the insulating film. A source electrode window and a drain electrode window are formed, then a silicon film is formed on the substrate to be processed having the insulating film, and then an MIS to which information is to be written is formed.
selectively removing the silicon film on the source electrode window of the transistor, then forming an aluminum film on the substrate to be processed having the silicon film, and then patterning the aluminum film and the silicon film below it; M.I.
A programming pattern is formed on the source electrode window of the S transistor, and a wiring pattern is formed on the drain electrode window, and then the substrate to be processed having the programming pattern and the wiring pattern is heated to create a MISI in which the information is to be written.
- It is characterized by having a step of short-circuiting the source region of the transistor and the semiconductor layer with aluminum.

The following is a process cross-sectional view of an embodiment of the present invention shown in FIGS. A detailed explanation will be given using a schematic top view of an MIS type mask ROM formed by the method of the same embodiment.

When forming a MIS type mask ROM by the method of the present invention, for example, a P-type silicon (Si) substrate is used, and the Si is An isolation region made of a feed oxide film having a P channel cut region below is formed on the substrate surface, and the isolation region separates the P-type Si substrate surface into a plurality of element forming regions.

Next, after forming a gate oxide film on the element formation region by, for example, thermal oxidation, chemical vapor deposition (CVD) is performed on the substrate.
A polycrystalline silicon layer is formed using a method such as a dry etching method, and a gate wiring made of polycrystalline silicon is formed on the gate oxide film by selectively etching the polycrystalline silicon layer using a dry etching method or the like.

Next, using the gate wiring and field oxide film as a mask, N type impurity ions are selectively implanted into the surface of the P type Si substrate in the element formation region to form an N + type source region and an N type source region to a depth of approximately 3000 to 5000 mm. Form a train area.

Figure 1a shows a MIS IC substrate on which multiple MIS transistors are formed on a Si substrate as described above. In the figure, 1 is a P-type Si substrate, 2 is a P-channel cut region. , 3 is a field oxide film, 4 is an isolation region,
5 is a gate oxide film, 6 is a polycrystalline silicon gate wiring,
7 is an N-type source region, 8 is an N-type drain region, 9a, 9
b indicates a MISI-transistor.

Next, as shown in FIG. 1, a phosphosilicate glass (PSG) film 10 with a thickness of about 1 to 2 [μm] is formed as an insulating film on the MIS IC substrate using a normal CVD method, and then The PS is etched using the usual dry etching method, etc.
All MIS transistor N-type source regions 7 in the G film 10
and forming a window exposing a part of the N-type drain region 8,
Next, the PSG film 10 is reflowed at a high temperature, for example, to form source electrode windows 11a, 11b and drain electrode windows 12 having a smooth to sloped opening.

Next, using a commonly used battering method or plasma CVD method, etc., the upper surfaces of the source region 7 and drain region 8 exposed in all the electrode windows on the substrate, the inner surfaces of the electrode windows, and the PSG are removed. For example, about 400 to 500 polycrystalline (or amorphous) silicon films 13 are formed over the entire region including the upper surface of the film 10.

The MIS IC substrate having the above structure is stored as a mask ROM forming substrate.

Next, in the method of the present invention, using the above-mentioned mask ROM forming substrate, the MISL/LAN disk 9a to which information is to be written is first prepared as shown in FIG.
polycrystalline (or amorphous) on the source electrode window 11a of
The silicon film 13 is etched by a conventional dry etching method using, for example, carbon tetrafluoride (CF4) or hydrofluoric acid (HF).
) Deca nitric acid ()TNO,') is selectively removed using a wet etching method using a liquid.

Incidentally, since the selectively removed region 14 can be formed wider than the opening dimension of the electrode window 11a, high precision is not required for alignment in the etching.

Next, as shown in FIG. 1d, for example 1 [
After forming a pure aluminum (Al) film 15 with a thickness of approximately 1 μm, and then forming an upper layer wiring pattern made of photoresist on the Al film 15, the photoresist pattern is used as a mask. , using a dry etching method, first A was etched using a halogen-based etching gas.
The polycrystalline (or amorphous) silicon film 13 is selectively removed using an etching gas such as CF4, and the MISI to which the information is to be written is removed as shown in FIG. 1e. - A programming pattern 16a in which the AA film 15 is in direct contact with the source region 7 is placed on the source electrode window 11a of the transistor 9a, and the A4 film 15 is made of a polycrystalline (or amorphous) silicon film on the other source electrode window 11b. 1 for the program that contacts the source area 7 through 13? The pattern 16b and each drain electrode window 12
A drain wiring 1 on which an Al film 15 is in contact with a drain region 8 via a polycrystalline (or amorphous) silicon film 13
form 7.

The substrate was then heated for 400 to 500 [
℃] and maintained for the desired time.

A7 of the programming pattern 16a formed on the source electrode window 11a of the MIS transistor 9a in which the information is to be written by the heat treatment penetrates deeply into the source region while diffusing the Si layer in contact with the pattern into the inside of the pattern. 7, short the junction and connect P
16'a is the intrusion area of A7 that reaches inside the type Si substrate 1)
, information is written.

In addition, at this time, the drain wiring 17 of each transistor and the programming AA pattern 16b of the transistor 9b in which no information is written had a polycrystalline (or amorphous) silicon film 13 interposed below, so the polycrystalline (or amorphous) silicon film 13 was ) The silicon film 13 is completely dissolved, and the depth of the Al penetration region that penetrates into the source region or drain region becomes extremely shallow, and the N-type source region 7, the N-type drain region 8, and the P-type Si substrate 1 The junction between them will not be destroyed.

MIS type mask ROM formed by the method of the above embodiment
Figure 2 shows the electrical equivalent circuit of the MIS transistor. MIS transistors are shown.

In the mask ROM, for example, with the substrate (the P-type Si substrate) sub grounded, a desired voltage is applied to the bit line B formed by the drain wiring,
In addition, when a voltage higher than the threshold voltage (Vth) is applied to the word line W formed by the gate wiring, in the MIS transistor T1 in which information is written, the source (S is short-circuited from the drain to the substrate). (indicating a short-circuit condition), and information appears on bit line B.

In addition, in the MIS transistor T2 to which no information has been written, even if a voltage higher than vth is applied to the word line W, the source junction is in a reverse bias state and is floating from the substrate, and has no circuit wiring. Therefore, no current flows through the transistor T2, and therefore the bit line B
information is not displayed.

FIG. 3 is a schematic top view of the mask ROM, in which 6 is a gate wiring, 9a is an MIS transistor in which information is written, 9b is an MIS transistor in which no information is written, 12 is a drain electrode window, 15 is the drain wiring, 1
6a shows a programming Al pattern with a short-circuited source junction, and 16b shows a programming Al pattern without a short-circuiting source junction.
One advantage of M is that the written information cannot be read from the top.

The steps up to information writing in the manufacturing method of the MIS type mask ROM of the present invention have been described for one embodiment. A mask ROM can be provided by simply going through these simple steps.

Therefore, according to the present invention, the number of steps required for manufacturing an MTS type mask ROM can be significantly shortened.

In the above embodiment, information was stored by shorting the source of the MIS transistor and the substrate.
In the case of C-MOS, etc., information is stored by short-circuiting the source and the P-well.

[Brief explanation of drawings]

1A to 1F are process cross-sectional views of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a MIS type mask ROM formed by the method of the embodiment, and FIG. FIG. 3 is a schematic top view of an MIS type mask ROM formed by the method. In the figure, 1 is a P-type silicon substrate, 2 is a P-channel
cut area, 3 is field oxide film, 4 is isolation area, 5
is a gate oxide film, 6 is a polycrystalline silicon gate wiring, and 7 is a gate oxide film.
8 is an N type source region, 8 is an N type drain region, 9a is an MIS transistor in which information should be written or has been written, 9b is an MIS transistor in which information is not written or has not been written, 10 is a phosphosilicate glass film, 11
a and 11b are source electrode windows, 12 is a drain electrode window,
13 is a polycrystalline silicon or amorphous silicon film;
14 is the selective removal area of 13, 15 is the aluminum film, 1
6 and 16b are aluminum patterns for programming,
16a is an aluminum penetration region, 17 is a drain wiring, sub is a substrate, B is a bit line, W is a word line, T1 and T2 are MIS transistors.

Claims (1)

[Claims] 1. An insulating film is formed on a substrate to be processed having a semiconductor layer on which a plurality of MIS transistors are formed, and then a source electrode window and a drain electrode window of the MISI transistor are formed on the insulating film, and then a A silicon film is formed on a substrate to be processed having an insulating film, and then the silicon film on the source electrode window of the MIS transistor to which information is to be written is selectively removed, and then an aluminum film is formed on the substrate to be processed having the silicon film. A film is formed, and then the aluminum film and the silicon film below it are patterned to form a programming pattern on the source electrode window of the MIS transistor and a wiring pattern on the drain electrode window. A method for manufacturing a mask ROM, comprising the step of heating a substrate to be processed having a pattern and a wiring pattern to short-circuit a semiconductor layer and a source region of a MIS transistor into which the information is to be written with aluminum.