JP2840321B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a mask ROM, and more particularly to a semiconductor device such as a mask ROM in which information is written depending on the presence or absence of a contact or a connection wiring. The present invention relates to a technique which is effective when applied to a transistor using a MOSFET or a MISFET as a configuration transistor.

(Prior art)

For the mask ROM, a contact code mask method or an ion implantation code mask method is used.
Considering (application-specific LSIs), writing information in the contact or metal wiring process can shorten the TAT (turn around time) for obtaining a ROM with the required information. .

As shown in FIG. 9, a memory cell in a conventional contact code mask type ROM has a word line WLi, connected to a gate electrode of a MOSFET Q1 constituting a memory cell transistor.
WLj is coupled to the power supply wiring 2 connecting the source electrodes of all the MOSFETs Q1 to the ground potential Vss of the circuit. Writing information to this memory cell is done by MOSFET
It is determined by whether or not the drain electrode of Q1 is connected to the bit line BLi. In other words, the connection element (the portion indicated by the double-dot chain line) marked for determining the logic of the memory cell data is the bit line BL.
Present on the i side. FIG. 10 shows a layout configuration example of the memory cell section. 4, reference numeral 4 denotes an aluminum wiring forming the bit line BLi, 5 denotes a gate electrode of the MOSFET Q1, and a polysilicon layer forming the word lines WLi and WLj.
An electrode is formed and also serves as the electrode wiring 2. In this layout configuration, the connection between MOSFET Q1 and bit line BLi is determined by the presence or absence of contact hole 6.

As an example of a document describing a contact code mask type ROM, there is Japanese Patent Publication No. 57-38034.

[Problems to be solved by the invention]

However, conventional contact code mask ROM
Since the logic of the stored information is determined by whether or not the drain electrode of the memory cell configuration MOSFET Q1 is connected to the bit line BLi, the number of MOSFETs Q1 connected to the individual bit lines differs depending on the storage content of the entire ROM, The MOSFET Q1
The parasitic capacitance caused by the gate-drain capacitance of each bit line becomes uneven between the respective bit lines. Such irregularities in the parasitic capacitance are as follows:
This causes non-uniformity in the change of the read signal level and the change speed on the bit line. Therefore, even in a ROM having a peripheral circuit having the same configuration, a situation in which an access speed is different depending on the stored content of the ROM may be caused, and in order to perform high-speed access, it is necessary to individually cope with the stored content. It is practically impossible to take such measures. Further, the inventor has studied a method of differentially amplifying a reference level read from a dummy cell and a read signal level from a bit line to read data at high speed. If the change in the read signal level on the bit line and the change speed change for each bit line, it may not be possible to take a certain margin for the difference between the reference level and the read signal level from the bit line. It is assumed that even if a differential sensor amplifier is used, a malfunction may occur or high-speed reading may not be performed as expected. To solve this problem, the parasitic capacitance of the bit line is determined irrespective of the stored contents. I found the need to keep it constant.

An object of the present invention is to make the parasitic capacitance of a bit line constant in a semiconductor device such as a mask ROM in which information is written in the presence or absence of a contact or in a metal wiring step, regardless of the storage content. Another object of the present invention is to increase the data reading speed in a semiconductor device such as a mask ROM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the drain electrode of the field effect transistor for memory cell configuration is connected to the bit line, and whether or not the source electrode of the transistor is connected to the power supply wiring, that is, the interlayer insulation is provided between the source electrode and the power supply wiring. Information is written depending on whether or not a film is formed.

From the viewpoint of shortening the TAT in a semiconductor device such as the mask ROM, the connection between the power supply wiring formed of the first metal wiring layer and the source electrode of the field effect transistor is changed. It is preferable to use a contact hole for connecting the constituent diffusion region and the metal wiring layer.

Further, in order to reduce the number of contacts for connecting the bit line and the memory cell transistor, the connecting means for connecting the bit line formed of the second metal wiring layer and the drain electrode of the field effect transistor must be adjacent. It is preferable that the field effect transistors be used in common.

In order to speed up the operation of selecting a memory cell transistor to increase the access speed, a third layer for transmitting a memory cell selection drive signal to a word line constituting a gate electrode of the field effect transistor is used. It is preferable to provide a metal wiring layer.

In order to speed up the operation of the sense system of the memory cell data, a dummy bit line is connected to a field effect transistor having a higher on-resistance than the field effect transistor, and the dummy bit line and the bit line are connected to each other. A differential sense amplifier that determines the memory cell data by differentially amplifying the potential difference of the differential sense amplifier may be employed, and the precharge level of the bit line may be applied to the differential input terminal of the differential sense amplifier. It is preferable to connect a level shift circuit that biases the amplification factor of the amplifier to a maximum level.

(Operation)

According to the above-described means, writing information depending on whether or not the source electrode of the memory cell transistor is connected to the electrolytic wiring means that the number of memory cell transistors connected to each bit line corresponds to the storage content. The operation is performed so as to be constant independently of each other, and the parasitic capacitance of the bit line is made constant regardless of the stored contents.

The fact that the bit line parasitic capacitance becomes constant irrespective of the stored contents means that the read signal level on the bit line and the speed thereof do not change regardless of which bit line is selected in data reading. Thus, the expected high-speed reading can be achieved without causing a malfunction by using a differential sense amplifier.

〔Example〕

FIG. 1 schematically shows a mask ROM according to an embodiment of the present invention. First, the entire mask ROM will be described with reference to FIG.

The mask ROM shown in the figure includes a memory cell array 11, a dummy cell array 12, a precharge circuit 13, a row address decoder 14, a column address decoder 15, a column selection circuit 16, a sense circuit 17, etc. It is formed on a semiconductor substrate.

The memory cell array 11 includes N-channel type MOSFETQ11 ₀₀ ~Q11nm for configuration memory cells in a matrix arrangement, the dummy cell array 12 includes one column of N-channel type MOSFETQ12 ₀ ~Q12n the dummy cell configuration. MOSFET Q12 _{0 to} Q1
2n its on resistance to be about half of about MOSFETQ11 ₀₀ ~Q11nm, for example the MOSFETQ12 ₀ ~Q12n channel width is generally in half MOSFETQ11 ₀₀ ~Q11nm. Said
MOSFETQ11 ₀₀ ~Q11nm, MOSFETQ12 ₀ gate electrode of ~Q12n is coupled to the word line WL ₀ ～WLn line by line, the word line WL
_{One of 0 to} WLn is driven to a selected level according to an output selection signal of a row address decoder 14 for decoding a row address signal RADDR. A drain electrode of the MOSFETQ11 ₀₀ ~Q11nm is coupled to the bit line BL ₀ ~BLm by columns,
The MOSFETQ12 ₀ ~Q12n drain electrode of which is coupled to one of the dummy bit line BLn. And the bit lines BL _{0 to} BLm
And the dummy bit line BLn is, P-channel type MOSFET Q13 ₀ contained before start of reading data to the precharge circuit 13
The voltage Vdd is supplied through Q13n.

Information storage for the memory cell is performed depending on whether the source electrode of MOSFETQ11 ₀₀ ~Q11nm is connected to a ground power source wiring 18. Therefore, MOSFETs Q11 _{00 to} Q12 nm
When the MOSFET whose source electrode is coupled to the ground power supply wiring 18 is selected and turned on,
The bit line to which the drain electrode is coupled is discharged via the ground power supply wiring 18. In addition, MOSFET
If a MOSFET whose source electrode is not coupled to the ground power supply wiring 18 is selected _from Q1 _{00 to} Q11 nm,
The bit line to which the drain electrode of the SFET is connected maintains the precharge level. For all dummy cell configurations
The drain electrodes of MOSFETs Q12 _{0 to} Q12n are ground power supply wiring 18
Is joined to.

The bit lines BL ₀ ~BLm is coupled to the common data line CD through the P-channel type MOSFETQ14 ₀ ~Q14m included in the column selection circuit 16. This common data line CD is coupled to one input terminal of the sense circuit 17,
A dummy bit line BLn is connected to the other input terminal of the transistor 17 via a P-channel MOSFET Q14n. Sense circuit 1
7 determines and outputs the logical value of the read data by differentially amplifying the level difference between the common data line CD and the dummy bit line BLn initialized to the power supply voltage Vdd level. Incidentally, the MOSFETQ14 ₀ ~Q14m column address signal
A predetermined one is controlled to be on according to an output selection signal of the column address decoder 15 for decoding CADDR, and the MOSFET Q14n is turned on in synchronization with the selection operation.

 Next, details of the memory cell will be described.

FIG. 2 shows a pair of MOSFETs Q11mm and Q11n for forming a memory cell in which the source electrodes are both coupled to the ground power supply wiring 18.
m is representatively shown. All memory cells constituting a MOSFETQ11 ₀₀ ~Q11nm drain electrode as described above is coupled to a corresponding bit line, as shown in ○ mark portion of the two-dot chain line, connecting the source electrode to the ground power supply line 18 The logical information of the memory cell data is determined depending on whether or not. Therefore, the parasitic capacitance of the bit lines BL ₀ ~BLm due to the drain-gate capacitance of MOSFETQ11 ₀₀ ~Q11nm is constant regardless of the information stored in the memory cell.

FIG. 3 is a plan view of the device structure corresponding to FIG. 2, and FIG. 4 is a cross-sectional view taken along line aa of FIG.

Reference numeral 21 denotes a diffusion region formed in a P-type semiconductor substrate (or P-type well region) 20, on which a polysilicon layer 22 and a first-layer aluminum 23 (23) are sequentially placed via an interlayer insulating film 25.
A), a second aluminum layer 24 is formed.

3 and 4, the polysilicon layer 22 constitutes the word lines WLm and WLn, and the portions overlapping the diffusion region 21 via the gate oxide film are the MOSFETs Q11mm and Q11.
nm gate electrode. According to the present embodiment, the diffusion region 21 located on the side of the gate electrode is implanted with N ⁺ impurities, and has a source electrode 26 of the MOSFET Q11 mm, a drain electrode 27 common to the MOSFETs Q11 mm and Q1 nm, and a source electrode 28 of the MOSFET Q11 nm. Is done. MOSFET Q11mm, Q11nm drain electrode 2
7 is connected to the first aluminum layer 223A via the contact hole 30 and the first aluminum layer 23A is connected to the second aluminum layer 24 via the through hole 31. The drain electrodes 27 of the MOSFETs Q11 mm and Q11 nm are connected to the second aluminum layer 24 forming the bit line BLm. The source electrodes 26 and 28 of the MOSFETs Qmm and Qnm are selectively connected to the first aluminum layer 23 constituting the ground power supply wiring 18 according to the logic information to be held by the MOSFETs Qmm and Qnm. In the example of FIGS. 3 and 4, both of the source electrodes 26 and 28 are connected to the first aluminum layer 23 through the contact holes 32 and 33.
It is connected to the.

As described above, in the mask ROM of the present embodiment, information of a required logical value is written depending on whether or not a contact hole represented by 32 or 33 is formed, so that the TAT can be shortened. Also, as represented by MOSFETs Q11mm and Q11nm, contact holes for connecting the drain electrodes and bit lines are provided.
Since the 30 and the through-hole 31 are shared between adjacent ones, effective use of space is achieved.

FIG. 5 illustrates an example in which the structure for transmitting the selection signal to the word line in the configuration of FIG. 3 is improved. In the configuration of FIG. 3, the word line drive signal of the row address decoder 14 is directly applied to the polysilicon layer 22, but in the example shown in FIG. , WLn, a third aluminum layer 35 for transmitting a memory cell selection drive signal is arranged. The connection between the polysilicon layer 22 and the third aluminum layer 35 is made by, for example, connecting the polysilicon layer 22 and the first aluminum layer 23B through a contact hole 36, as shown in FIG. First aluminum layer
The second aluminum layer 24A is connected to the second aluminum layer 24A through the through hole 37, and the second aluminum layer 24A is connected to the third aluminum layer 35 through the through hole 38. As described above, the word line selection drive signal is achieved at the gate electrode of the MOSFET for forming the memory cell via the third aluminum layer 35 having a lower resistance than the polysilicon layer 22, so that the memory cell selection operation is accelerated. .

FIG. 7 shows an example of the sense circuit 17. Although not particularly limited, the sense circuit 17 includes a level shift circuit 40 coupled to the common data line CD and the dummy bit line BLn, and a sense amplifier 41 receiving output signals D1 and D2 of the level shift circuit 40. .

The level shift circuit 40 includes, but is not limited to, a pair of N-channel MOSFETs Q23 and Q24 in a differential form.
And another pair of N-channel MOSFETs Q25 and Q26 provided on the source side of these MOSFETs. The drain electrodes of MOSFETs Q23 and Q24 are coupled to the supply voltage Vdd of the circuit,
The commonly coupled source electrodes of MOSFETs Q25 and Q26 are connected to the circuit ground potential V via an N-channel drive MOSFET Q27.
Combined with ss.

The gate electrode of MOSFET Q23 is connected to the common data line CD,
Then, the gate electrode of MOSFET Q24 is coupled to dummy bit line BLn. The gate electrode of MOSFET Q25 is coupled to its drain and is further commonly coupled to the gate of MOSFET Q26. As a result, the MOSFETs Q25 and Q26 are in a current mirror form.

Control signal φsa is applied to the gate of drive MOSFET Q27. The control signal φ is a control signal for activating the level shift circuit 40 and the sense amplifier 41 in the data read operation, and is set to a high level in response to the data read. Source potentials of the MOSFETs Q23 and Q24 are supplied to the sense amplifier 41 as output signals D1 and D2. The control signal φ is not particularly limited, but is also used as a control signal for the precharge circuit 13.

The level shift circuit 40 thus configured is brought into an operating state when the control signal φ is set to a high level. At this time, the bit lines BL _{0 to} BLm and the dummy bit lines BL
n is precharged to the power supply voltage Vdd level in advance through the precharge circuit 13 operated by the low-level control signal φ. Therefore, the power supply voltage Vdd or a signal that changes from the power supply voltage Vdd to the ground potential Vss according to the state of the memory cell selected by the word line is applied to the common data line CD as shown in FIG. Can be For example pre-charge level of the common data line CD in the case where the source electrode and MOSFETQ11 not connected to a ground power source wiring 18 ₀₀ is selected (power supply voltage Vdd)
And the source electrode is grounded
Etc. and are MOSFET Q11 ₁₀ which is connected to 18 the voltage signal changes from the power supply voltage Vdd on the common data line CD to the ground potential Vss is applied to the case chosen. At this time, as shown by the dashed line in FIG. 8, a signal that changes from the power supply voltage Vdd toward the ground potential Vss at half the change speed on the common data line CD is applied to the dummy bit line BLn as shown by the broken line in FIG. . Individual MOSFE
TQ12 ₀ ~Q12n on-resistance of MOSFETQ11 for configuration memory cell ₀₀
This is because it is set to about twice as large as Q11 nm. As described above, the level shift circuit 40 is supplied with a differential voltage that changes from the power supply voltage Vdd as a starting point from the common data line CD and the dummy bit line BLn.
And Q24 are both turned on. Therefore, MOSFETQ
The source potentials of 23 and Q24, that is, the output signals D1 and D2 are
It changes in phase with the voltages of the common data line CD and the dummy bit line BLn around a predetermined bias level determined by the conductance of the ETQ23 and Q25 and the conductance of the MOSFETs Q24 and Q26.

In this embodiment, the bias level is not particularly limited, but is set at a substantially intermediate level between the power supply voltage Vdd of the circuit and the ground potential Vss, that is, Vdd / 2. In the present embodiment, the bias level Vdd / 2 matches the level at which the sensitivity of the sensor amplifier 41 is maximized.

Although not particularly limited, the sense amplifier 41 includes a pair of N-channel MOSFETs Q30 and Q31 in a differential form, and a pair of P-channel MOSFETs provided on the electrode side of these MOSFETs.
And MOSFETs Q28 and Q29. The source electrodes of MOSFETs Q28 and Q29 are coupled to the supply voltage Vdd of the circuit, and MOSFETs Q30 and Q3
An N-channel drive MOSFET Q32 is provided between one common-coupled source electrode and the circuit ground potential Vss. The gate electrode of MOSFET Q28 is coupled to its drain electrode and further to the gate electrode of MOSFET Q29.
Thus, MOSFETs Q28 and Q29 are in the form of a current mirror. Output signals D1 and D2 of the level shift circuit 40 are supplied to gate electrodes of the MOSFETs Q30 and Q31, respectively. The control signal φ is supplied to the gate of the drive MOSFET Q32.

The drain potential of MOSFET Q31 is further supplied to the input terminal of CMOS inverter circuit 42 as internal signal D3. There is no particular limitation between the input terminal of the inverter circuit 42 and the power supply voltage Vdd of the circuit, but a P-channel type preset MOSFET receiving the control signal φ at its gate electrode.
Q33 is provided. This preset MOSFET Q33
The ROM is turned on when the control signal φ is at a low level in the ROM chip non-selection state, whereby the output of the sense circuit 17 is undefined while the sense amplifier 41 is inactive and the chip is not selected. Is prevented.

When the mask ROM according to the present embodiment is set to the chip selection state, the control signal φ is set to a high level in response to this,
The sense circuit 17 is activated. At this time, a signal having a voltage as shown in FIG. 8 is supplied to the level shift circuit 40 from the common data line CD and the dummy bit line BLn.
The level shift circuit 40 has a bias level for each input voltage.
Output signals D1 and D2 to which Vdd / 2 is applied are applied to the sense amplifier 41. As described above, the sense amplifier 41 is designed so that the amplification factor is maximized at the bias level Vdd / 2, and when the difference between the signals D1 and D2 increases, the signal D2
The voltage difference of the signal D1 with respect to the signal Q1 is expanded and taken out as the drain voltage of the MOSFET Q31. The drain voltage of MOSFET Q31 is inverted and amplified by inverter 42, and is read out from a data output buffer (not shown) as a signal having a logical value corresponding to the information stored in the memory cell.

 According to the above embodiment, the following operational effects are obtained.

(1) all memory cells constituting a MOSFETQ11 ₀₀ ~Q11nm drain electrode of which is coupled to a corresponding bit line, and logical information of the memory cell data is determined by whether or not to connect the source electrode to the ground power supply line 18 I have. Therefore, it is possible to a parasitic capacitance of each bit line BL ₀ ~BLm due to the drain-gate capacitance of MOSFETQ11 ₀₀ ~Q11nm constant regardless of the information stored in the memory cell.

(2) Due to the above operation and effect, no matter which bit line is selected, the level of the common data line CD and the level of the dummy bit line BLn given to the level shift circuit 40 are relatively set as shown in FIG. Are changed so as to be sequentially enlarged with a predetermined difference. Therefore, the signals D1 and D2 applied from the level shift circuit 40 to the sense amplifier 41 are also changed with the same difference voltage, so that the logical value of the memory cell data can be accurately determined without error. In other words, since a constant voltage margin can be secured between the reference level given from the dummy bit line BLn and the read signal level given from the common data line CD, it is not erroneous to judge the logical value of the read data. Absent.

(3) Since the drain electrodes of the MOSFETs for configuring the memory cells are coupled to all the bit lines, the parasitic capacitance of the bit lines is set to a constant value with a relatively large value. Is applied through a level shift circuit 40 that shifts the precharge level to the maximum level, so that the logic determination and amplification of the data read from the memory cell are performed. Can be speeded up.

(4) the connection between the source electrode of the ground power supply line 18 and the memory cell structure for MOSFETQ11 ₀₀ ~Q11nm made by the first-level aluminum layer 23, and source electrode configuration for the diffusion region 21 of the transistor and the aluminum layer 23 Can be shortened by the contact holes 32 and 33 that connect the above, so that the TAT in the mask ROM can be shortened.

(5) Bit line BL made of second aluminum layer 24
_By sharing the connection means between _{0 to} BLm and the drain electrode of the memory cell configuration MOSFET between the adjacent memory cell configuration MOSFETs, the number of contacts for connecting the bit line and the memory cell transistor is reduced. Can be reduced.

(6) By providing a third aluminum layer 35 for transmitting a memory selection drive signal to the word lines WL _{0 to} WLn forming the gate electrodes of the memory cell configuration MOSFET, the memory cell transistor selection operation is performed. Can be accelerated.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

In the above description, the case where the invention made by the present inventor is mainly applied to a mask ROM as a single memory chip, which is the application field in the background, has been described, but the present invention is not limited thereto, and The present invention can be widely applied to a one-chip microcomputer incorporating such a memory, a logic LSI having a ROM array such as a programmable logic array, and the like. The present invention can be applied to at least a condition for storing information depending on the presence or absence of a contact or a wiring.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the drain electrode of the field effect transistor for memory cell configuration is connected to the bit line, and information is written depending on whether the source electrode of the transistor is connected to the power supply wiring. The number of memory cell transistors connected to each bit line becomes constant irrespective of the stored contents, thereby providing an effect that the parasitic capacitance of each bit line can be easily equalized.

By making the bit line parasitic capacitance constant irrespective of the stored contents, the read signal level on the bit line and the speed thereof do not change regardless of which bit line is selected in data reading. . Therefore, when a differential sense amplifier that differentially amplifies the reference level read from the dummy cell and the read signal level of the memory cell is used, it is necessary to accurately determine the logic value of the memory cell data without error and read it out. The effect that can be obtained.

Further, when using a differential amplification type sense amplifier, a level shift circuit that biases the precharge level of the bit line to a level at which the amplification factor of the sense amplifier is maximized is connected to the differential input terminal of the sense amplifier. This makes it possible to further speed up the logic determination and amplification operation of the memory cell data by the sense amplifier.

In addition, the connection between the power supply wiring and the source electrode of the field effect transistor is made by a contact hole, so that the TAT in the mask ROM can be reduced.

Further, by sharing the connection means between the bit line and the drain electrode of the field effect transistor between adjacent field effect transistors, the number of contacts for the connection can be reduced.

By providing a third metal wiring layer for transmitting a memory cell selection signal to a word line forming a gate electrode of the field effect transistor, a memory cell transistor selection operation can be accelerated.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a mask ROM according to an embodiment of the present invention, FIG. 2 is a detailed example circuit diagram of two bits of memory cells, and FIG. 3 is a device structural diagram corresponding to FIG. FIG. 4 is a cross-sectional view taken along line aa of FIG. 3, FIG. 5 is a plan view of a device structure in which an aluminum wiring is connected to the word line of FIG. 3, and FIG. FIG. 7 is a plan view of an example of a connection portion between a word line and an aluminum wiring in the figure, FIG. 7 is a circuit diagram of an example of a sense circuit, FIG. 8 is an operation explanatory diagram of the sense circuit, and FIG. FIG. 10 is an example circuit diagram of a memory cell. FIG. 10 is a plan view of the device structure of FIG. 11 …… Memory cell array, 12 Dummy cell array, 13 ……
Precharge circuit, 17 Sense circuit, Q11 _{00 to} Q11 nm
... memory cell configuration for MOSFET, Q12 ₀ ~Q12n ...... dummy cell configuration for MOSFET, WL ₀ ~WLn ...... word lines, BL ₀ ~BLm ...... bit line, BLn ...... dummy bit line, CD ...... common data line, 18 ... Ground power supply wiring, 21 ... Diffusion area, 22 ...
Polysilicon layer, 23 first aluminum layer, 24
… Second aluminum layer, 30, 32, 33 contact hole, 31 through hole, 35 third aluminum layer, 40 level shift circuit, 41 sense amplifier.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Satoshi Shinagawa 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-LSE Engineering Co., Ltd. (72) Masao Mizukami, Ome, Tokyo 2326 Imai Ichi, Japan Device Development Center, Hitachi, Ltd. (56) References JP-A-57-160153 (JP, A) JP-A-53-121529 (JP, A) JP-A-56-147473 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 17/12

Claims (1)

(57) [Claims] A first field-effect transistor including a drain electrode connected to a bit line and an interlayer insulating film formed between a source electrode of the transistor and a power supply line; A memory cell in which information is written by a dummy bit line to which a second field-effect transistor having a higher on-resistance than the first field-effect transistor is connected; and a dummy bit line and a bit line. A differential sense amplifier for determining memory cell data by differentially amplifying a potential difference between the differential sense amplifier and a differential input terminal of the differential sense amplifier, and setting a precharge level of the bit line to the differential A level shift circuit for biasing the amplification factor of the type sense amplifier to a maximum level.