JPS5846955B2 - Inverter parallel operation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a load sharing control device in an inverter parallel operation device.

In uninterruptible power supplies that use inverters, multiple units are operated in parallel to improve the reliability of the system, and when any inverter fails, the failed inverter is disconnected from the load and other healthy inverters are used. A method that supplies stable power to a load has become common.

To perform parallel operation, it is necessary to correct imbalances in load sharing caused by irregularities in the control circuits of each inverter and deviations in the internal impedance of the main circuit. Means is adopted to control the voltage difference between the inverters and the phase difference between each inverter using the deviation of the active power.

Since the present invention relates to the improvement of the latter method of controlling the phase difference using the deviation of the active power, a conventional device for controlling the active power will be explained with reference to FIG.

In the figure, 10 is a reference oscillator, whose output is the delay circuit IL
They are added as 21 reference voltages, respectively.

Inverters 12 and 22 are operated in parallel, and their output terminals are connected together to the common bus 16 and their outputs are combined to supply alternating current power to the load 100.

13.23 is an active power deviation detection circuit, and current transformer 14.2
4 and a transformer 15.25 to each inverter 12.25.
22 active powers are detected respectively, and each inverter 12, 2
The active power deviation between the two delay circuits 11 and 21 is
as a control signal.

FIG. 2 shows an example of the delay circuit 11.21.

In this figure, 30 is an integrator that can be reset every cycle; 35
is a comparator between the inverter 36 and the signal coupling point 37,
38 is a set output Q when 1'' is input to the set terminal S.
occurs, and when "1" is input to the reset terminal R, an R-S flip-flop produces a reset output Q. Reference numeral 39 is a mono-multi-bi-break that produces a rectangular wave output of a constant width every time a trigger input is input.

The reference pulse signal A is applied to the set terminal S of the R-S flip-flop 38, and the control signal port or 8 is applied to the connection point of the comparator 35.

The operation will be explained with reference to FIG. 2 and FIG. 3 which is a time chart thereof.

When the reference pulse I from the reference oscillator 10 is applied to the set terminal S of the R-S flip-flop 38, the reset terminal Q output is inverted and becomes "091", so that the FET (field effect transistor) 33 in the integrator 30 turns off.

The integrator 30 uses a constant human power 31, a resistor 32, and a capacitor 34.
Integration is started with a time constant determined by .

That is, when the R-S flip-flop 38 is reset, the FET 33 of the integrator 30 is turned on and the capacitor 34 is short-circuited, so the voltage is zero, but when the R-S flip-flop 38 is set, it starts integrating, and its polarity is reversed. Therefore, the output H decreases linearly.

The comparator 35 matches the output H of the integrator 30 with the control signal port (or C), and when the output H of the integrator 30 is larger than the control signal port (or C), the output is inverted to R-S. A reset signal is sent to the reset terminal R of the flip-flop 38.

When the R-S flip-flop 38 is reset by this reset signal and its reset terminal Q output becomes "1", the FET 33 in the integrator 30 is turned on and the charge in the integrating capacitor 34 is discharged.

The output of the comparator 35 is "1" for a short period when the output H of the integrator 30 is again equal to the control signal port (or C).
becomes.

If the waveform of the output of the R-S flip-flop 38 is shaped by a mono multivibrator 39, a delayed pulse can be obtained.

As can be seen from the above, the delay time of the ignition pulse of the inverter 12.22 is controlled by the magnitude of the control signal port (or C).

In other words, a delay time corresponding to the magnitude of the control signal is obtained such that the control signal is small, T is large when the control signal is 1 value, and T2 is the control signal is binary. However, in this case, the maximum value Tm of the delay time cannot exceed the period τ of the reference pulse I, and Tm≦
There is a relationship of τ.

By the way, in FIG. 1, the repetition frequency f of the reference oscillator 10.

is generally an integral multiple of the inverter 12.22 output frequency f, and there is a relationship of fo=Nf (N is a positive integer).

Therefore, the phase angle that can be controlled by the delay circuit 11.21, that is, the delay time, is 3.
60°÷N, and as a typical example, when N=12, it is 30
°.

As mentioned above, the causes of active power imbalance are due to misalignment of the control circuits and deviations in the internal impedance of the main circuit, but especially when the control circuit systems of the inverter 12 and inverter 22 are different, or the capacitance of the main circuit If they are different,
With a control width of 30°, it is not possible to sufficiently correct deviations in active power, and as delay circuits 11 and 21, multiple circuits shown in Fig. 2 are connected in series (if two are connected in series, 30° x 2 = 6
0').

Furthermore, it is necessary to provide exactly the same frequency reference to the delay circuits 11 and 21, and the reference oscillator 10 is connected to the inverter 12,
There is an essential drawback in that it cannot be provided exclusively for each of the 22 devices.

In other words, for the purpose of increasing reliability, the number of parallel inverters is 3.
Even if 6 or more oscillators are connected in parallel, the reference oscillator 10
This will affect the reliability of the system, and there will be a limit to how much reliability can be improved.

In view of this point, an object of the present invention is to provide a parallel operation device for inverters with a control configuration that is not limited at all to the control width of the phase angle, even though the phase difference is controlled by the deviation of the active power of each inverter. do.

An embodiment of the present invention will be described below with reference to FIG.

Components in FIG. 4 with the same reference numerals as in FIG. 1 have the same functions, so a description thereof will be omitted.

The difference between FIG. 4 and FIG. 1 is that two reference oscillators of 10-1°10-2 are provided for exclusive use, and a delay circuit of 11°21
instead of a phase-locked loop (phaselock
ed 1oop) So-called PLL circuits 11' and 21' are provided, and output phase detection transformers 1B and 2B are further provided to feed back the output phase signal to the PLL circuits 11' and 21'.

Here, since the PLL circuits 11' and 21' are well-known technologies, a brief explanation will be given.
1' is shown as a general usage example.

In the figure, 10' is an oscillator, 19 is a ring counter, and 11' is a PLL circuit.
Consists of CO.

To give an overview of each of these elements, the phase error detector PH
D generates a voltage S proportional to the phase difference between the phase reference signal Q and the phase feedback signal WO.

FIG. 6 shows the gain characteristics of this phase error detector PHD.

A voltage proportional to this phase difference is input to a low frequency wave generator LPF, which removes harmonic components and amplifies the phase error.

As this low-pass filter LPF, as shown in FIG. 7, a well-known proportional-integral circuit consisting of an operational amplifier A1, resistors R1o and R11, and a capacitor C1o may be used.

Then, the high-voltage controlled oscillator vCO outputs a frequency proportional to the output of the low frequency waveform generator LPF, and this voltage-controlled oscillator ■C
The output of O is connected to the ring counter 19.

If the number of stages of the ring counter 19 is N, the oscillation frequency of the voltage controlled oscillator VCO is N times that of the oscillator 10'.

As mentioned above, the output of the ring counter 19 serves as one input of the phase error detector PHD, that is, the phase feedback signal.

Therefore, the oscillation frequency of the voltage controlled oscillator (1) CO is automatically controlled so that the phases of the phase reference signal (1) and the phase feedback signal (2) coincide.

Here, if the phase angle is θ and the frequency is f, the frequency f is defined by differentiating the phase angle θ with respect to time t, and f=aO.

Conversely, the integral value of the frequency f is the phase angle t becomes.

That is, if the frequency is controlled by the phase error, the phase error will be integrated, and there is no limit to the control width of the phase angle.

Now, in Fig. 4, two reference oscillators are used, and even if a crystal oscillator is used as the oscillator, the difference in frequency between the reference oscillators 10-1 and 10-2 is about 0,001%, and this frequency The difference is the lateral phase difference (this phase difference is 0°
(changes by an amount of 360° from the phase angle), which results in a deviation of the active power, but in the conventional method, there are limitations during phase angle control, so control becomes impossible.

However, in the present invention, since the active power deviations and C are fed back to the PLL circuits 11' and 21' having the above-mentioned functions, the phase difference between the oscillators 10-1 and 10-2 and the control circuit of the inverters 12 and 22 are It is possible to correct deviations in active power caused by irregularities in the main circuit and main circuit impedance without limit.

In order to feed back the deviation of the active power to the PLL circuit, as shown in FIG. 8, an operational amplifier A of the low-frequency F wave device LPF in the PLL circuit 11' or 21' is used.

It is only necessary to add an active power deviation to the voltage via the resistor R12, and the operational amplifier A1o automatically controls the output frequency, that is, the phase, of the voltage controlled oscillator VCO so that the active power deviation becomes zero.

As described above, in the present invention, since deviations in active power can be corrected without limit, a reference oscillator can be individually provided for each inverter, and the reliability of the system can be improved.

If the purpose is simply to widen the phase angle control period, such as when inverters with different capacities (main circuit impedances differ significantly) are operated in parallel, the reference oscillator 10 can be changed as shown in FIG. It may be common.

As described above, in the present invention, in order to control the phase difference by the deviation of the active power between each inverter, a phase-locked loop is provided as an automatic phase control element between the reference oscillator and the inverter, and this phase-locked loop is effective. Since the power deviation is added, it is possible to provide an inverter parallel operation device that is free from restrictions during phase angle control.

[Brief explanation of drawings]

Figure 1 is a block circuit diagram of an inverter parallel operation device using a conventional active power control method, Figure 2 is the delay circuit in Figure 1, Figure 3 is a time chart of the delay circuit in Figure 2, and Figure 4 is the main A block circuit diagram of one embodiment of the invention, FIG. 5 is a block circuit diagram explaining a PLL circuit of the same embodiment, and FIG.
Characteristic diagram of the phase error detector of the LL circuit, Fig. 7 is a circuit diagram of the low-frequency p-wave device of the PLL circuit, Fig. 8 is a side diagram of the circuit that adds deviation of active power to the low-pass p-wave device, and Fig. 9 is a block circuit diagram of another embodiment. 10.10-1.10-2,10'...Reference oscillator, 11,21...Delay circuit, 11', 12
'... PLL circuit, 12, 22... Inverter, 13, 23... Active power deviation detection circuit, 14, 24... Current transformer, 15 .25...
...Transformer, 1B, 2B...Output phase detection transformer, 100...Load.

Claims (1)

[Claims] 1. In an inverter parallel operation device that controls the phase difference based on the difference in active power between each inverter, a phase-locked loop is provided as an automatic phase control element between a reference oscillator and each inverter, and this phase-locked loop An inverter parallel operation device that adds the deviation of active power to . 2. The inverter parallel operation device according to claim 1, wherein a reference oscillator is individually provided for each inverter. 3. The inverter parallel operation device according to claim 1, wherein only one reference oscillator is provided for each inverter in common.