JPS5847065B2 - identification logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an identification logic circuit that is effective for use in an information matching circuit of a character reading device or the like.

The configuration of the verification section of a character reading device is generally as shown in FIG.

That is, as shown in FIG. 1A, signals output from the optical section and the feature extraction circuit section 11, which are composed of sections 11 and 12, are input to the matching circuit section 12 that performs character matching.

The comparison result is then output as an output signal of the character reading result obtained by the character reading device.

FIG. 1B shows the configuration of this verification circuit portion in more detail.

In the figure, the human input ■ indicates a feature sequence obtained by the feature extraction circuit in the character reading device, and the input ■ indicates a prepared R
OM (Read-only) Indicates the contents (dictionary) stored in the memory.

These feature strings and the contents stored in the ROM memory are transferred to the matching circuit 13 and bit-matched.

In other words, each of the plurality of bits constituting the feature string is
It is compared with the corresponding bits in memory, and if all the corresponding bits are the same, a match code is output as the reading output of the character reading device, and if there is a mismatch, a reject code is output.

The present invention provides a feature sequence obtained by the feature extraction circuit,
This relates to the information retrieval section 13 that compares the contents stored in the ROM memory, that is, feature sequences prepared for verification.

FIG. 2 explains the configuration of a data comparison circuit in such an information retrieval section.

In the figure, the data string represented by human power (■) indicates the feature string obtained by the feature extraction circuit.

Among these, a signal "1" represents that a meaningful feature exists at that position in the feature sequence, and a signal "0" represents that a meaningful feature does not exist at that position.

The signals "1" and "0" both have the same weight.

Furthermore, data strings represented by human power (■) indicate feature strings prepared as dictionaries.

The signals "1" and "0" each represent the same meaning as the signal representing the feature sequence obtained by the feature extraction circuit.

The comparison circuit shown in FIG. 2 compares the contents of the two feature strings indicated by the inputs ``■'' and ``■'' on a bit-by-bit basis, and the arrows in the figure indicate this comparison.

By the way, when comparison is performed pit by pit in each feature string in this manner, there are actually bits for which the comparison is not very important and bits for which the comparison is important.

Therefore, it is desirable to be able to freely specify locations where comparison is necessary or unnecessary during verification.

In fact, in most character reading devices, it is necessary to divide the feature string into bits to be compared and bits not to be compared. There is no degree of freedom in the feature sequence, and if you try to recognize characters using this matching method, you will have to create an almost infinite number of dictionaries in advance.

For this reason, the data string (mask data) indicated by input ■ in FIG. 2 is provided to set the comparison method during signal verification.

In this manual operation (2), a normal comparison of signals is performed in the column where the signal "1" exists.

That is, in this case, if the corresponding bits of the manual input (2) and the input (2) are the same signal, the output (2), which indicates that the comparison results are the same, will not appear.

The case where the corresponding bits are the same is, for example, a case where the inputs ``1'' and ``2'' are both the signal "1" as in the column indicated by the symbol "■" in FIG. 2, or a case where these inputs are both the signal "O".

On the other hand, in the column where the signal "0" exists in the input (2), an output appears indicating that the comparison results are the same whether or not the signals of the input (2) and the input (2) are the same.

That is, in this case, a "match" output is simply output regardless of both signals (don't care).

For details, the signal of input ■ is "1", and the signal of input ■ is "0"
The comparison result is the same even in the case where the signal of the input (2) is "O" and the signal of the input (2) is "1".

In this way, the signals at each position of the aircraft are compared, and when all comparison results are determined to be the same,
A reading result indicating that the content matches the dictionary content is output as an output code.

In other words, if the comparison results are the same, a signal ``1'' is output, and if the difference is -, a signal ``0'' is output, then when the AND of all comparison results is a signal ``1'', it is the same as the contents of the dictionary. This means that the characters have been recognized.

Such a mask data string corresponds to the data string of the dictionary and each bit.

For example, if the data string of the dictionary is 100 bits, it has a corresponding mask data string of 100 pits.

In other words, such a character recognition method uses a dictionary composed of a 2-bit dictionary data string corresponding to each bit of the feature string of the input (2).

FIG. 3 shows an example of a circuit for comparing signals at each position of a feature string.

The numbers ■ to ■ in the figure indicate the verification, verification method instruction, input, and output signals, as in FIG. 2.

In an actual matching circuit, as many circuits as shown in FIG.
The reading result will be output from the output terminal of the D circuit.

Now, the operation of the circuit shown in FIG. 3 with respect to the position indicated by the symbol ■ in FIG. 2 will be explained as follows.

Since the human power ■ to ■ are both signals "1", the signal "O" is output from the NOR circuit 31, and the signal "0" is output from the inverter 32.
is input to the NOR circuit 33.

Therefore, the output of circuit 33 is 1, and matching circuit 340
Signal "1" is input to both input terminals and the result is output■
A signal "1" appears.

The above operating logic and the operating logic when other signals are input are collectively shown in FIG. 4.

Numbers .about.1 in the figure have the same meanings as the numbers in FIG.

In this circuit, the comparison method is not specified only by the mask data (input 2), but the inputs 2 and 2, that is, the dictionary data string and the mask data string are combined to give one instruction.

That is, when ■ and ■ are 010, it is a don't care, and regardless of whether the feature column ■ is 1 or O, the output ■ is 1, that is, a match, and when the inputs ■ and ■ are 0 and ■, it is an inverter. The feature sequence 0°1 is converted to an output of 1.0.

When the inputs (2) and (2) are 1, O or 1, (2), a simple buffer is specified, and the feature sequence O11 is passed through to the output O11.

By the way, as is clear from the above explanation, in the conventional circuit for collating feature strings, the dictionary requires a memory capacity of 2 bits for 1 bit of the feature string.

However, in the conventional identification logic circuit as shown in Fig. 3,
The four states that can be constructed from the 2-bit data in this dictionary are not effectively utilized for the 1-bit data in the feature string to be compared.

That is, from the 2-bit data, the dictionary records "state 1" of the signal "0.0", "state 2" of the signal "Oll", "state 2" of the signal "1,"
It can take four states: "state 3" of "0" and "1 state 4" of signal "1.1", but as is clear from Fig. 4,
“State 1” don’t care (
(Don't Care), it is an inverter for "state 2", that is, input ■, and furthermore, "state 3" and "state 4" output the same answer to output ■ for input ■. , so to speak, corresponds to the state as a buffer, and after all, the dictionary consists of 2 bits of data (for 1 bit of the feature string of input ■), which are the mask data and the feature string of the dictionary, so the input ■ , ■ can represent four states, the output ■ is the input ■, ■
It only represents three states compared to the four states of .

In other words, even if the mask data represents don't care, if the feature string of the dictionary and the feature string of the identification target do not match, it is not considered a match match.

The present invention improves this point by making it possible to obtain four output states for the four possible states of the dictionary memory, which is composed of 2 bits for each 1 bit of the input feature sequence. The object of the present invention is to use the memory effectively in this way, fully utilize the data stored in the dictionary memory, and provide flexibility in the criteria for checking against the dictionary.

That is, the identification logic circuit of the present invention has a first logic circuit section and a second logic circuit section, and is configured to obtain two types of logic outputs from the same input signal.

The second logic circuit portion is configured such that the condition for determining a match is stricter than that of the first logic circuit portion.

This result is used as the comparison result until the output of the second logic circuit part (that is, the second logic circuit part always outputs the matching result as a match for the bits of the feature string where the mask data is don't care). In addition to providing flexibility in information retrieval, the accuracy of information retrieval can also be expressed by the appearance order of which logical circuit parts are outputting matching outputs with the same comparison result.

Hereinafter, the present invention will be explained in more detail along with examples.

FIG. 5 shows an identification logic circuit according to the first embodiment;
The figure is a diagram showing its operational logic.

In the figure, the human inputs (1) to (2), the output (2), and the first logic circuit portion 51 are completely the same as the logic circuit shown in FIG.

The circuit of the present invention shown in FIG. 5 further includes a second logic circuit portion 5.
2 are provided, and the inputs (1) to (2) are signal-branched and input to the two-ring circuit portions 51 and 52.

Therefore, inputs ■ and ■ from the same dictionary yield outputs ■ and ■.

Now, the inputs ■ and ■ input to the circuit of FIG. 5 are content descriptions of input characters and matching characters, respectively, and there is no redundancy as such.

Therefore, in the present invention, redundancy is provided by the description content of input (2) and two different logic circuits.

In this circuit, the output ■ and the output ■ show different values in the parts A and B marked with an asterisk (→) in FIG.

In these cases, the inputs ■, ■, and ■ are signals "1" and "1", respectively.
"0" and "O".

In this case, the signal rlj rOJ is input to the NAND circuit 53 of the second logic circuit 52, and the signal rlj rOJ is input to the NAND circuit 53 of the second logic circuit 52.
The signals rOJ and IOJ are input to 4, so the outputs of these circuits are both 11'', which is input to the matching circuit 55, and as a result, a signal ``1'' appears at output 4.

On the other hand, the signal appearing at the output (2) from the first logic circuit 51 is "0", similar to the output circuit shown in FIG.

Therefore, the dictionary data■. For the two states 0.1 of the character feature string and input ■, whose features were extracted in state 3 of ■ ``1, O'', the answer of output ■, which is the matching result, is ``0.1''.
” and “1゜1”, so conventionally,
In the four input states of the dictionary data, there were only three answers to the input ``O'', but in this embodiment, four answers can be obtained.

In this case, the second logic circuit portion 52 outputs a weaker comparison result than the first logic circuit portion 51.

In other words, the output ■ is ++ 111 only when the input ■ is 1''.
(match) is not output, whereas the output (2) outputs 1'' whether the input (2) is 0'-u 1 H.

Therefore, if the reading result is the logical sum of the signals of outputs ■ and ■, a sweeter recognition result can be obtained, and moreover, output ■.

Priority can be given to the reading results depending on the state of the signal (2).

FIG. 7 shows an identification logic circuit according to a second embodiment of the present invention, and FIG. 8 is a diagram showing its operational logic.

In the figure, the human inputs (1) to (2), the outputs (2) and (2), and the second logic circuit portion 52 are exactly the same as the logic circuit shown in FIG.

In this circuit, the circuit configuration of the first logic circuit portion 510 is different.

Enter this■、■. ■ is the signal “1”, rol,
To explain the case where it is "0", the AND circuit 71
And the signals “1” and “
0” is input.

As a result, the signal "O" is input to the NOR circuit 730 input terminal, and the signals rOJ and "1" are input to the AND circuit 740 input terminal.

As a result, the signals appearing at the output terminals a and b of these circuits become "1" and "0", respectively, and since these signals are input to the OR circuit 75, a signal "1" appears at its output (2).

In the logic circuit 52 of the second option, a signal "1" appears at both the output terminal C of the NAND circuit 53 and the output terminal d of the NAND circuit 54 due to the logic operation described above, and as a result, the output (■) of the -number circuit 55 becomes The signal "1" appears.

Looking at FIG. 8, for example, among the operation logic tables obtained in this manner, the following becomes clear.

First, the output (2) of the first logic circuit has the same logic for the input (2), which is a characteristic input, in "state 2" and "state 3".

Also, the output ■ of the second logic circuit is "state 1" and "state 3"
The same is true for .

Therefore, in the first logic circuit, "state 1", "state 2", "state 3" and "state 4" are respectively set by "x" (
Don't care), "0" (matches when input signal ■ is 0)
, "O" (match when the input signal ■ is O), and "1" (match when the input signal ■ is 1), then the second logic circuit's matching concept is "×", " 0”,
“x” and “1”.

Therefore, this identification logic circuit states, ``If state 3j is excluded, outputs ■ and ■ are both ``×'', ``O'', and ``1'', and ``state 3''.
"0" when the pressure is ■, "×" when the output is ■
It can be seen that

If a mask for matching is created by setting this "state 3" to [loose "0"], even if there is no matching output as a comparison result from output (2), matching can be performed so that a matching output is output from output (2).

In this way, in the present invention, the outputs of the comparison results (■, ■) for the feature string of the 2-bit dictionary can take four states, so the capacity of the dictionary memory can be used effectively, and the input (■, In the comparison result ■ and ■ for state 3 "1, O" in ■, the output ■ represents a softer comparison result than the output ■, so it is possible to improve the recognition performance of the reading device, and especially the reading result Paste errors or errors can be corrected without re-reading.

Note that the logic circuits used in the present invention are not limited to those shown in the embodiments, and can be freely selected and combined within the tolerance required for identification.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the verification section of a character reading device, Fig. 2 is an explanatory diagram of a conventional data comparison circuit, Fig. 3 is a conventional identification logic circuit, and Fig. 4 is an illustration of the circuit shown in Fig. 3. FIG. 3 is an operational logic diagram. 5 and subsequent figures show embodiments of the present invention, and FIG.
6 is an operational logic diagram of the circuit shown in FIG. 5, FIG. 7 is an identification logic circuit in the second embodiment, and FIG. 8 is an operational logic diagram of the circuit shown in FIG. Show the diagram. In the figure, 51 is the first logic circuit, 52 is the second logic circuit, ■ is the verification signal, ■ is the verification method instruction signal, ■ is the input signal, ■ is the output of the first logic circuit 51, and ■ is the first logic circuit. 2 shows the output of the logic circuit 52 of No. 2.

Claims (1)

[Claims] 1 Consists of a group of logic circuit elements, and includes an input signal to be identified, a verification signal prepared in advance in memory, and a control signal that weights the verification signal and instructs a verification method. A first logic circuit section that receives the input signal and outputs the first match determination result, and a logic circuit element group that receives the input signal, the verification signal, and the verification method instruction signal and outputs the first match determination result. The second condition is sweeter than the matching condition.
An identification logic circuit comprising a second logic circuit portion that outputs a matching result of a match determination condition.