JPS584771B2 - Weight Checker - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a weight checker that can check a plurality of types of articles having different weights.

The details will be explained with reference to an embodiment shown in the accompanying drawings.

In a weighing machine consisting of a conveyor 1 for sending in an article to be weighed A, a conveyor 2 for weighing the article A, and a conveyor 3 for sending out, an analog of the article A to be weighed is weighed by the weighing conveyor 2. An analog-to-digital converter 4 converts the weight value AI into a digital weight value D1, and the digital weight value D1 output from the analog-to-digital converter 4 is used as an address designation signal S to output the lower limit value D2 of the weight value. It includes a first memory 5 and a second memory 6 which outputs the upper limit value D3 of the weight value from the address designation signal S, and each of the first and second memories 5,
First and second comparators 7 and 8 are provided to compare each output value of 6 and the digital weight value.
a logic circuit 9 for determining the output content of each comparison output signal from 8;
Holding circuits 10 and 1 for each signal output from the logic circuit 9
1 and 12 to constitute a means for outputting excessive amount, correct amount, and insufficient determination signals P1, P2tP3.

The comparator 7 compares the digital signal D1 of the detected weight with the output lower limit value D2 from the first memory 5, and the output state is DI>D2, DI
=D2, D1<D2, and the comparator 8 compares the digital signal D1 of the detected weight with the output upper limit value D3 from the second memory 6, and the output is D.
There are three outputs: I>D3, DI=D3, and DI<D3.

Further, as for the logic circuit 9, the outputs D1>D2 and DI=D2 of the comparator 7 are input to the OR gate 16, and the outputs Di<D3 and D1=D3 of the comparator 8 are input to the OR gate 17. each of the or gates 16,
17 outputs Q1 and Q2 are input to an AND gate 18, and the output Q3 of the AND gate 18 matches the output signal Q4 from the position detector 20 provided at an appropriate position on the weighing conveyor 2. A circuit that holds the holding circuit 11 with the output signal Q5 and outputs the positive amount signal P2;
When the output DI<D2 of the comparator 7 and the output signal Q4 of the position detector 20 match, the holding circuit 12 is set to hold by the signal Q6 outputted via the AND gate 15, and the circuit outputs the shortage signal D3. , the output of comparator 8 DI>D
3 and the output signal Q4 of the position detector 20, the holding circuit 1 is outputted through the AND gate 13.
It is comprised of a circuit that holds and sets 0 and outputs an excess signal P1.

Furthermore, 21 in the figure is an amplifier for the detected weight signal A1, and 22
is a display portion of the detected weight value, and R is a reset signal, and this reset signal R is configured to be output with an appropriate delay time after the detection signal Q4 is output from the position detector 20. Ru.

19 is a range setting for dividing the value of the digital signal D1 into several ranges and determining the address S when inputting the digital signal D1 as an address designation signal S to each of the first and second memories 5 and 6; It is a circuit.

For example, a circuit that determines an address S for each value of <DI, such a circuit can be easily constructed using a known calculation method.

The present invention has the above configuration, and its operation will be explained next.

First, the articles A to be weighed are irregularly fed into the feeding conveyor 1 in an random order and are weighed by the weighing conveyor 2.

Therefore, when the analog weight value A1 generated by the measurement is output, the weight value A1 is
The signal is amplified by 1 and input to the next analog-to-digital converter 4, where it is converted into a digital value D1 of the measured weight.

Further, the signal D1 is input to the first memory 5 and the second memory 6 as an address designation signal S through the range setting circuit 19, and from the first memory 5, a preset weight is inputted. The lower limit value D2 is output, and the second memory 6
From then on, the upper limit value D3 of the weight will be output.

That is, as in the example shown in FIG.
5], the lower limit value D2, 1.190 (g) is output from the first memory 5 according to the address specification.
Also, from the second memory 6, upper limit values D3, 1, 210C, F
) for each output.

By the way, each of the first and second memories 5 and 6 is a read-only memory ROM and a read-write memory RA.
M, etc. are adopted, and the upper limit value D3 and lower limit value D2 guaranteed by the value of the address signal S are set in advance.

Of course, it is also possible to easily configure D3, D2, etc. to be manually variable using a daisy switch or the like.

Incidentally, both the lower limit value D2 and the upper limit value D3 output from the first and second memories 5 and 6 are output as digital values.

Therefore, the output digital value D1 from the analog-to-digital converter 4 is input to one terminal of each of the next first and second comparators 7 and 8, and the output lower limit value D2 of the first memory 5 is is input to the other terminal of the first comparator 7, and the first comparator 7 compares the digital value D1 of the detected weight with the lower limit value D2.

Further, the output upper limit value D3 of the second memory 6 is inputted to the other terminal of the second comparator 8, and the digital value D1 and the upper limit value D3 are inputted.
This results in a comparison of .

Therefore, as shown in FIG. 2, the first comparator 7 outputs the falling state of DI>D2, D1=D2, and DI<D2, and the second comparator 8 outputs D1>D3. ,D
Either I=D3 or DI<D3 is output.

That is, when the digital value D1 is equal to the lower limit value D2, or when it is larger than the lower limit value D2, the output is
DI=D2, DI>D2 are output and OR gate 16
is inputted to one terminal of the next AND gate 18 through.

Also, if the digital value D1 is smaller than the upper limit D3,
Or, if they are equal, the output is DI=D2, D
I>D2 is outputted, passes through the OR gate 16, and is inputted to one terminal of the next AND gate 18.

If the digital value D1 is smaller than or equal to the upper limit value D3, the output is Di<D3. D.I.
=D3 is outputted and inputted to the other terminal of the AND gate 18 through the OR gate 17.

The conditions for each output to be output through each of the OR gates l6 and 17 are that the detected weight value is the lower limit value D2 and the upper limit value D3.
It became clear that it was within the range of and.
An output signal Q3 is output from the gate 18, and when the signal Q3 matches the signal Q4 outputted from the position detector 20 when the article A to be weighed reaches an appropriate position on the weighing conveyor 2, an AND signal is generated. A signal Q5 is outputted from the gate 14, and the holding circuit 11 holds the output signal Q5, so that a positive amount signal P2 is outputted.

Further, when the output of the first comparator 7 is DI<D2, it is determined that the weight value is even smaller than the lower limit value, and as it matches the output signal Q4 from the position detector 20, the AND game is performed. A signal Q6 is outputted from the gate 15, held by the holding circuit 12, and a signal P3 corresponding to the shortage is outputted.

Next, when DI>D3 is output from the second comparator 8, it is determined that the weight value is even larger than the upper limit value, and a signal Q4 is outputted via the AND TATE 13 in agreement with the above signal Q4. Then, the holding circuit 10 is held by the signal Q4, and the signal P1 corresponding to the excess amount is output.

In addition, each holding circuit 10, 11, 12 is a reset signal that is output via an appropriate delay circuit (not shown) so that the output signal Q4 from the position detector 20 is output with a predetermined delay time. The hold is released by signal H.

As described above, the present invention detects the weight of the article to be weighed A, and the lower limit value D2 and upper limit value D3 are set based on the signal value, and the actual detected weight value is included between the lower limit value D2 and the upper limit value D3. To determine whether or not the weight is weighed, the correct weight signal P2, overweight signal P1, and low weight signal P3 are output, and the quality of the weight is determined for each weighed article. Various types of goods can be identified according to the number of address settings.
It has the advantage of being able to continuously check the weight of a wide variety of products, such as those packed in bags and boxes, using one device.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram showing the configuration of the present invention, FIG. 2 is a control block diagram of the present invention, and FIG. 3 shows the relationship between the address signal S, upper limit value D3, and lower limit value D2 in the same operation as above. This is a chart showing. DESCRIPTION OF SYMBOLS 1... Feeding conveyor, 2... Measuring conveyor, 3... Feeding conveyor, 4... Analog-digital converter, 5... First memory, 6... Second memory, 7... First comparison section, 8... Second comparison section, 9.
...Logic circuit, 10, 11, 12...Holding circuit, 13
, 14, 15, 18...and gate, 16, 17
...OR gate, 19...Range setting circuit, 20
... position detector, 21 ... amplifier, 22 ... weight display section.

Claims (1)

[Claims] 1. In a weighing machine consisting of a conveyor for sending in an article to be weighed, a conveyor for weighing the article, and a conveyor for sending out, the analog weight value of the article to be weighed by the weighing conveyor is converted into a digital weight value. an analog/digital converter that converts the digital weight value into a digital weight value, a first memory that outputs the lower limit value of the weight value by using the digital weight value output from the analog/digital converter as an address designation signal, and It is equipped with a second memory that outputs the upper limit value of the value, and the first and second
a logic circuit for determining the output content of each comparison output signal from the comparator; Configure a holding circuit for each signal output from the
A weight checker for sorting a plurality of articles, characterized in that the weight checker is configured with a means for outputting a determination signal of overload or shortage.