JPS5847730B2 - Memory access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for performing memory access from a channel control device, and particularly relates to a method for accessing a memory from a channel control device, and in particular, the present invention relates to a method for performing memory access from a channel control device, and in particular, to
This relates to improving memory latency in CW read operations.

The channel control device here performs control of a plurality of channels, and among these, there is control called command chaining.

This means that if a chain command is specified in the flag field defined in a CCW, when the data transfer indicated in that CCW is completed and a completion report is sent to the channel from I/O, the channel will move to the next CCW. is read from the memory, and 2/0 is activated again without intervention from the central processing unit to execute the next CCW.

FIG. 1 shows a memory access path including a channel control device.

1 represents a memory, 2 a central processing unit, and 3 a memory control unit.

Channel controllers are 4 and 9, 4 is channel 5-8
9 is a channel side memory control unit that buffers memory requests corresponding to each bank, 9 is a startup/interrupt control unit, and interface 13 is a channel side memory control unit that buffers memory requests corresponding to each bank.
This is to read out the data.

The interface 14 is used when 9 activates channels 5 to 8.

Interrupts from each channel to 9 also use this interface.

For deco transfer from memory to I/O using channel 5, data passes through the route 1→3→4→5→19.

For data transfer from I/O to memory, 19→5→
Data flows from 4 to 3 to 1.

When a channel executes a command chaining operation, the CCW read time is the largest among the time consumed by the channel.

In particular, for a channel connected to a disk having a rotating mechanism, the command chain time is defined by the gap length, and command chaining must be performed within this time.

It is also possible to read the CCW in advance, but this is because command chaining is instructed to the currently executing CCW, and this CCW's command is Read, and the next CCW is read into memory for the first time by this command. Preemption has no meaning in programming.

Therefore, reducing the CCW read time of the channel control device as much as possible contributes to faster execution of channel command chaining.

Taking the example of the prior art shown in FIG. 1, it is the startup interrupt control unit 9 that issues a CCW read request to the memory 1, but this request passes through a total of three priority circuits in 4 and 3. I have to.

In the memory control unit 3, the priority of memory requests is given to the channel control unit higher than that of the central processing unit, and in the memory control unit 4, the priority is set to CCW read requests from 9 to 5 to 8.
The data transfer request is set higher than the data transfer request of the channel in order to read the CCW quickly, but when there is a first-arrival load, even if the priority is set high, the CCW is kept waiting.

First-arrival load is rough; if a channel is using 4 or 3 buffers, it means that the request will have to wait until the first-arriving memory request has finished processing, even if it has a high priority. .

An object of the present invention is to eliminate the above-mentioned conventional problems, and to eliminate C from a channel control device.
The object of the present invention is to provide a device that gives top priority to CW reading, reduces memory waiting time, and reduces the influence of load caused by first-arriving memory requests.

The feature of this invention is that within the channel control device, priority is not given between memory requests for CCW reading and memory requests for other channels; It processes in parallel with the memory controller, provides a direct interface to the memory controller, takes priority within the memory controller,
It processes memory requests.

Since the memory control device prioritizes CCW read requests, it is possible to prevent the buffer from being used in advance due to channel writing/reading and having to wait for CCW reading.

FIG. 2 is a block diagram in a case where the CCW is configured to be read quickly.

The difference from the conventional example shown in FIG. 1 is that 23 in addition to 12 are provided as an interface between the channel side memo IJ/IJ quest control section 4 and the memory control device 3.

For example, if the interface 12 is a memory access in units of 8 bytes, the bus 4 to 3 is 8 bytes, 3
It has an 8-byte bus from 4 to 4, and the address line is several bytes from 4 to 3 (the value is determined by the memory capacity).

) configured to be sent.

23 is for sending an address line from 4 to 3 for CCW reading.

The memory control device receives two requests, a normal access request and a CCW read access request, from the channel control device.

3 to 6 show details of each section 4 and 3.1 in FIG. 2.

FIG. 3 shows the configuration of the buffer of the channel side memory request control section 4.

Assuming that the memory has 4 banks, 30, 31
Banks 0, 32, and 33 are buffers corresponding to banks 1, 34, and 35, and banks 2, 36, and 37 are buffers corresponding to bank 3.

38 is a buffer for temporarily storing CCW read data.

39-42 are 8-byte buses from channels 5-8, and 43 is a bus with the activation/interrupt control unit 9 in FIG.

``Therefore, the buffers 30 to 38 are 8 bytes here because memory access is performed in units of 8 bytes.

Another input to the buffer is bus 46 from the memory controller.

When reading from the memory, the output of the buffer passes through 47 and has one route for returning to each channel or activation/interrupt control section, and the other route is a bus 49 for sending data to the memory control device 3.

45.49 indicates a priority circuit.

45 narrows down to one bus from each channel and any device in the startup/interrupt control unit, and connects the buffers 30 to 3.
7.

Further, 49 is a priority level that determines which data in the buffer is to be sent to the 8-byte bus 48 to the memory control device 3.

FIG. 4 shows the structure of an address range register corresponding to each buffer shown in FIG.

Buffers 30, 31 and address 70.71, buffers 32, 33 and address 72.73, buffer 34
．． 35 and address 74. 75 is 36. 3
7 and addresses 76 and 77 respectively.

The input is the address line 79 sent from each channel.
.about.82 and an address line 83 sent from the startup interrupt control section 9.

Outputs are 85 and 86, and both address lines go to the memory controller.

The feature here is that the address line 86 for reading CCW
is sent to the memory controller independently of address lines 85 corresponding to other banks.

FIG. 5 shows the buffer configuration of the memory control device.

Buffers 90 to 93 receive data sent from the channel control device corresponding to each bank.

94 to 97 are buffers for memory writing, and 102
.about.105 is a buffer for reading from memory.

106 is a buffer for sending read data to other devices.

98 to 101 are memories, bank 0, bank 1,
Corresponds to bank 2 and bank 3.

As an input, an 8-byte bus 1 from the channel controller
08 (48 in FIG. 3) and an 8-byte bus 107 from the central processing unit.

The output of 106, 113, is an 8-byte data bus sent to the channel controller or central processing unit.

FIG. 6 is a block diagram showing the structure of addresses in the memory control device.

Registers 120 to 123 store addresses received from the channel control device, and correspond to bank 0, bank 1, bank 2, and bank 3, respectively.

124 is a CCW read-only address register.

One of these is provided regardless of the bank.

Address registers 125 to 128 correspond to memory banks.

Inputs are address 129 from the central processing unit, address 130 from the channel control unit, same < CCW address 1
It is 31.

Outputs OA-3A are connected to the memory banks of FIG. 5, respectively.

Reference numeral 110 in FIG. 6 indicates a priority circuit.

The memory control unit centrally controls the four banks, but here, requests from the central processing unit and requests from the channel control unit as well as CCW from the channel control unit are
Six of the reads are processed by priority.

In FIG. 2, there are basically two accesses to the memory 1 from the perspective of channels 5 to 8 and the activation/interrupt control unit 9: reading and writing.

A read request from channel 5 to bank 0 would be as follows.

First, when a request for channel 5 is accepted by the memory control unit, buffer 30 in bank 0 in FIG. 3 becomes in use, and an address is stored in address register 70 in FIG. 4 via interfaces 79 and 84.

The next time a read request is issued from the channel controller to the memory controller, the contents of address register 70 are stored in address register 120 through interface 85, through 130 in FIG.

The contents are then transferred to address register 125 and read from memory 98 in bank 0 of FIG.

The read data is stored in the buffer 30 via the buffer registers 102 and 106, the interface 113 in FIG. 5, and the interface 46 in FIG.

This data passes through interface 47 to channel 5.
If the buffer in bank 0 is in use, it will be canceled.

The buffer 31 for bank 0 is provided so that even when the buffer 30 is in use, the next request from the channel is accepted and the memo IJ IJ quest is constantly issued to the memory control device.

A write request from channel 5 to bank 0 would be as follows.

First, when a request from channel 5 is accepted by memory control unit 4, write data is stored in buffer 30 of bank 0 in FIG. 3 through interface 39.

The buffer 30 is in use at that point.

Further, the address is stored in the address register 70 of FIG. 4 via the interface 79.84.

When a write request is issued from the channel controller to the memory controller, the contents of address register 70 are stored in address register 120 via interface 85, through 130 in FIG.

It is further transferred to 125.

The data also passes through the interface 98 in FIG.
The data is stored in the buffer 90 shown in the figure.

This data is then transferred to buffer 94 in bank 0.

In this way, data 94 is written to the address indicated by the address register 125.

When the writing is completed, the memory control unit notifies the channel control unit of the completion, so at this point the buffer 3
0 is released from being in use.

To read the CCW, a request is issued from the activation/interrupt control section 9 in FIG. 2 to the memory control section 4.

When this request is accepted, the read buffer 38 of FIG. 3 is placed in use.

The address is passed through the interface 83 in FIG.
8.

This operation is performed in parallel even when the buffers 70, 71, etc. are in use, for example.

When a CCW read request is issued from the channel controller to the memory controller, the contents of address register 78 are stored into address register 124 from interface 131 in FIG. 6 through interface 86.

If the bank for CCW reading is 0, the address is transferred from 124 to 125, and reading is performed from memory 98 in bank 0.

The read data passes through the buffer registers 102 and 106, passes through the interface 113 in FIG. 6, and is stored in the buffer 38 via the interface 46 in FIG.

This data is transmitted to the activation/interrupt control section 9 through the interface 47.

And while 38 is in use, it will be canceled. In Figure 3, C
When the buffer 38 for CW reading is in use, it is easy to control the buffers 30 to 37 to be used.

Further, although the buffer 38 is provided in only one stage in FIG. 3, it is also possible to have two stages so that the CCW can be read out continuously.

With the structure described above, the following effects can be obtained in the present invention.

1. In CCW reading, priority is directly determined by the memory control device, so at least the buffer 30~
There is no need to wait for the CCW to be read while the CCW is being used.

2. CCW reading is not made to wait due to the priority circuit 49 of FIG.

Because of the above-mentioned effects, it is expected that the time required for reading the CCW will be reduced by several times compared to the conventional memory access control method.

In particular, with channels 5-8 operating - i.e.
Effective when memory usage is high.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional memory access path.
FIG. 2 is a diagram showing an embodiment of the memory access control method according to the present invention, and FIG. 3 is a diagram showing a buffer configuration of a memo IJ IJ quest control section in a channel control device. FIG. 4 is a diagram showing the structure of an address register within the channel control device. FIG. 5 is a diagram showing the buffer configuration of the memory control device. FIG. 6 is a diagram showing the structure of addresses within the memory control device. 1...Memory, 2...Central processing unit,
3...Memory control device, 4...Memo I
J IJ Quest control unit (inside channel control device), 5~
8... Channel, 9... Startup/interrupt control unit (inside channel control device), 10... Memory control device-memory interface, 11...
・Interface between central processing unit and memory control unit, 1
2...Memory control device-channel control device interface, 13-18...Internal interface, 19-22...I/O interface,
23...Memory control device 1 channel control device interface (for CCW reading), 30-38...
...Data buffer (inside channel control device), 39~
42...Interface between channel and memory request control unit, 43...Interface between startup/interrupt control unit and memory request control unit, 44...
...Data bus, 45...Priority circuit, 4
6... Interface between memory control device and memory request and quest control section, 47... Interface between memory request control section 1 channel/activation interrupt control section, 48... Memory request control Part 1 Memory control device interface, 49...Priority circuit, 70-78...Address register (inside channel control device), 79-82...39-42
Same as 83... Same as 43, 84...
・Address bus, 85...Same as 46, 86・
...Same as 46, 90-93...Data buffer (in memory control unit), 94-97...
・Data buffer (in memory control unit), 98-101
... Memory, 102-105 ... Data buffer (for reading), 106 ... Interface data buffer, 107 ... Central processing unit - memory control Inter-device interface, 108...
...Memory control device-channel control device interface, 109...Data bus, 110...
・Priority circuit, 111...Data bus, 112
．．・．． ...Priority circuit, 113...Memory control device-channel control device interface, 120-
124...Address register (in the memory control device), 125-128...Address register,
129... Ink face between central processing unit and memo IJ IJ Quest control device, 130, 131...
...Memo! J Control device 1 channel control device interface, 132...address bus.

Claims (1)

[Claims] 1 In an information processing system in which memory requests from the central processing unit and channel control device are made to the memory control device, and memory write/read operations are performed under the control of the memory control device, the channel control device performs data write operations to the memory. , a set of control units for read operation;
A set of control units dedicated to reading control information from the memory is provided, and these two interfaces are provided from the channel control device to the memory control device, and the priority for memory access in the memory control device is determined from the central processing unit.
The configuration is such that the write/read requests from the channel control device are set high, and the read-only requests from the channel control device are set higher than the write/read requests, so that the read operation of control information in the channel control device is given top priority. A memory access control method featuring: