JPS5847785B2 - Buffer-memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a buffer storage device in a computer operated under the management of a multi-structured operating system.

In general, recent computer operating systems tend to use several types of operating systems in a multilayered structure, creating a need for a buffer control method that achieves the optimal page size for each operating system.

The configuration of the buffer memory in current medium-sized computers is as shown in Figure 1, and in the figure, the buffer memory has the same address capacity as the directory.
Data is transferred to and from the main memory in units of one block, and whether or not the required data exists in the buffer memory is determined by address inquiry to the directory.

Buffer memory is 4 banks x 64 columns or 4 banks x
It is configured as 128 columns, and a block is the minimum unit of data transfer and is configured as 32 bytes, 64 bytes, etc.

The page size is buffer memory capacity is 4 banks x 64
Buffer memory accesses must be performed using real addresses, such as 2K bytes for columns and 4K bytes for 4 banks x 128 columns, and in systems that use virtual memory, buffer accesses are performed in parallel with address conversion. Since it is efficient to do so, it is customary to perform buffer access using bits that are not address translated.

Therefore, when the page size is 2K bytes, the buffer addresses (columns) are limited to a maximum of 64 columns, and when the page size is 4K bytes, the buffer addresses (columns) are limited to a maximum of 128 columns.

Here, in a multiplexed structure of operating systems with different page sizes, when the page size changes from, for example, 4K bytes to 2K bytes when migrating from a higher operating system to a lower operating system, the buffer storage capacity also changes to the page size. In a buffer memory composed of 4 banks x 128 columns, it must be reduced to 4 banks x 64 columns.

Conversely, when migrating from a lower-level operating system to a higher-level operating system, the page size and buffer storage capacity also shift to larger sizes, contrary to the previous example.

At this time, the issue is the validity of the address for the increase in the buffer memory, and in general, conventional methods indicate the validity of the data in the flag bit of the deink tree that corresponds to each address in the buffer memory. By resetting the valid bits for all addresses for the buffer storage increment, all 4 banks of addresses x 128 columns of buffer storage can be made available.

Another method is to apparently fix the capacity of the buffer memory to half and use it as 4 banks x 64 columns, but this method does not allow the full functionality of the upper operating system to be utilized.

Furthermore, in the former case, the number of addresses is large and the reset time is considerably long in resetting the flag bit of the increased address, so both of these two methods have drawbacks.

In view of the above, the present invention aims to eliminate the above-mentioned drawbacks of the conventional technology, that is, even if the required buffer storage capacity changes due to a change in page size, no extra reset time is required, and the optimum buffer storage capacity is achieved. It is an object of the present invention to provide a means for detecting transitions in the direction of page size expansion, and counting transitions in at least one direction, when different page sizes transition to each other depending on the operating system. A counter and a flag bit section are provided in a directory corresponding to each address of the buffer memory, and each time a new write is made to the buffer memory after the page size changes, the contents of the counter are transferred to the flag bit section of the directory and stored. In this manner, when reading the contents of the expanded portion of the buffer memory corresponding to the expansion of the page size after the page size has transitioned in the expansion direction, the contents of the directory and the contents of the counter are compared. This is achieved by a buffer storage control method characterized by having means for determining the validity of the contents of the buffer storage.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, BD is a directory that stores address contents and flag bit ID for buffer storage index.
is a buffer memory, DR is a buffer memory read register, WS is a buffer write register, WD is a directory write register, ADR is a logical address register, TSR is a register that stores real addresses converted by an address translation mechanism. The TLB is a storage device that stores the contents of the TSR and obtains the real address without address translation when the same logical address is accessed.

First, reading the buffer memory will be explained step by step.

The lower bit l2 of the logical address register ADR is the real address, which is used for buffer storage BS and directory B.
D is sent as an address input and each is read out.

The upper bit l1 of ADH is converted from a logical address into a real address by an address conversion mechanism TLB1TSR to become a real address l2', which is compared with a real address l3 read from the directory by a comparison circuit CM1.

Furthermore, as the page size transitions in the direction of expansion, directory B is
The data stored in the flag bit ID of D and the output l5 of the operating system status identification counter CTR are compared in the comparison circuit CM2, and when they match, the real address is determined by the logical address indicated by the logical address register ADH. The contents of the buffer memory are finally read out to the buffer read register DR.

Here, it is assumed that an identification counter CTR is incremented in accordance with the state of the operating system, and the count number is stored in the flag bit ID of the directory BD, as shown in FIG.

That is, the identification counter CTR receives the operating system status signal l4 and detects, for example, a transition from a small page size to a large page size by the detection circuit DC, so that it is known that the buffer storage BS has been expanded. , counted by identification counter CTR.

At this time, there is no problem in counting transitions from a small page size to a large page size, or counting transitions in both directions.

Here, when the upper operating system has a page size of 4K bytes and the lower operating system has a page size of 2K bytes, the transition from lower to higher is counted, and the buffer memory was operated at 2K bytes. When the operating system is expanded to 4K bytes, an identification counter CTR is used to store the above count results as a means of identifying the validity of each address for the expanded 2K bytes.
Each time the contents of the file are newly written to each address of 2K bytes in the expanded buffer memory, the contents are written as the flag bit ID of the corresponding directory.

Note that it is also possible to write the contents of the counter CTR to a 4-kilobyte address in the direct 1-IJBD, and to enable the comparator circuit CM2 only when it is read from the expanded 2-kilobyte buffer storage BS.

When writing to the buffer memory, there is no problem of identifying validity as proposed here, and it is only necessary to refer to the directory, search for an empty address in the buffer memory, and write.

Operating system state identification counter CTR
When writing to the directory L-IJ-BD, when writing to the buffer-memory BS, write to the directory BD corresponding to the address of the buffer-memory BS.
Write as flag bit ■D via D.

This write control can be handled in the same way as the directory address field and other control bits, so it does not affect the time required for buffer writing.

If the identification counter CTR overflows, there is a method in which the capacity of the buffer memory is fixed at 4 banks x 64 columns and returns to the initial state when the counter is reset by a system reset. The expanded half of the 64th to 127th
Each flag bit ID of the directory corresponding to the column
There is a way to reset it programmatically, but it would be nice to be able to select one or the other depending on the circumstances.

Furthermore, although this article describes a dual structure operating system with upper and lower layers, even in a multilayer structure with various operating systems with different page sizes, page size transitions can be detected and counted with an identification counter. By writing the content as a flag bit in the directory and checking it when reading the buffer, it is possible to determine the validity of the data read from the buffer.

As described above, according to the present invention, even if the page size changes in a multi-structured operating system, by comparing flag bits and counter output only when data is read from a buffer 1/1 unique extension part, the optimal It becomes possible to provide a large buffer storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the page size and structure of a buffer storage device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram of an identification counter. PU...External device, BS...Buffer memory, BD...Directory, WD...
...Directory write register, DR...
・Buffer read register, ADR...Logical address register CTR...identification counter,
DC...detection circuit, CM1, CM2...
・Comparison circuit, ■D...Flag bit, TLB,
TSR...address translation mechanism, l1...
- Logical address section output, l2. l2'...Real address part output, l3...Directory address part output, l4...Operating system status signal J'5...Identification counter output, l6
...Identification flag confirmation signal, l7...Buffer-memory read gate signal, l8...Write register output, l9...Buffer-memory output.

Claims (1)

[Claims] 1. A buffer that is located between a processor and a main memory that allows the operation of a multiplexed structure of operating systems with different page sizes, a directory, and a buffer and a storage controller that controls these. means for detecting a transition in the direction of page size expansion, a counter, and a flag bit section in the directory, the counter detecting at least one direction of transition when different page sizes transition to each other depending on the operating system; Each time a new page is written to the buffer memory after the page size changes, the contents of the counter are counted.
After the page size has transitioned to the expansion direction, when reading out the contents of the expansion part of the buffer memory corresponding to the expansion of the page size, the contents of the expansion part of the buffer memory corresponding to the expansion of the page size are transferred and stored in the flag bit part of the IJ-. 1. A buffer storage control system comprising means for comparing the contents of a flag bit part of the buffer with the contents of the counter to determine the validity of the contents of the buffer storage.