JPS5847794B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device suitable for a bipolar high-speed semiconductor memory circuit.

A memory cell in which a transistor having a plurality of emitters, that is, a combination of two multi-emitter transistors, occupies a small area when integrated into a circuit, is suitable as a memory cell for a large-capacity semiconductor memory device.
An example of a memory cell using this is shown in FIG.

In the figure, a memory cell M includes multi-emitter transistors Ql and Q2 having two emitters, and the collectors of each transistor Ql and Q2 are connected to a load resistor Rl.
, R2, and are connected in common to the power supply terminal C1 through a resistor R3.

Further, the collectors of the transistors Ql and Q2 are each cross-connected to the base of the other, and the first emitters of the transistors Ql and Q2 are commonly connected to the emitter drive terminal E1 for memory cell selection, and the second emitters of the transistors Q1 and Q2 are each connected to the emitter drive terminal E1, which will be described later. It is connected to an amplifier S1t82 for writing and reading.

A flip-flop circuit as one memory cell is thus formed.

The second emitters of the transistors Q1 and Q2 are commonly connected to the second emitters of transistors constituting a plurality of other memory cells, but this is omitted in FIG. 1 for the sake of simplicity.

The write/read amplifiers S1 and S2 are composed of transistors Q3 and Q4 and Q5 and Q6, respectively, which constitute a differential amplifier, and the emitters of Q3 and Q4 and Q5 and Q6 are connected in common to the transistors Q1 and Q2, respectively. Second
The emitter is connected to power supply terminals E2 and E3 via resistors R5 and R7 that define the read current or write current of memory cell M, and transistors Q3 and Q5
The collectors of are connected to output terminals TI and T2, respectively, and grounded via resistors R4 and R6.

In addition, the bases of transistors Q3 and Q5 have a reference voltage V
ref is applied, and an input signal VWo tVWx for information writing is applied to the bases of transistors Q4 and Q6.

Next, its operation will be explained.

The selection of memory cell M is based on the voltage VX of collector power supply terminal C1.
This is done by keeping o constant and setting the voltage EVX1 of the emitter drive terminal E1 to a low level when not selected and to a high level when selected.

In this case, it is assumed that the transistor Q1 is cut off and the transistor Q2 is in a conductive state, and the respective collector voltages are assumed to be c1 and c2.

When the memory cell M is in a non-selected state, that is, when the emitter drive voltage E does not flow.

Therefore, the current R flowing through the emitter resistor R7 of the write/read amplifier S2 flows through the resistor R7 rather than the transistor Q5, so the output voltage Vout of the transistor Q5 is Vout = V cc - α - R6 ° R where α:
Only a low electric current, indicated by the common base current amplification factor of the transistor, appears.

Note that each operating current flowing through resistors R5 and R7 has the same current value.
Set to R.

Next, when the memory cell M is in the selected state, that is, the emitter drive voltage 8EVx1 of the terminal E1 is at a high level, the transistor Q
2, the current R flows into the emitter resistor R7 of the write/read amplifier S2, so the current flowing through the collector resistor R6 decreases, and the voltage at the output terminal T2 rises to ``1''. ” information is read out.

Note that since the transistor Q1 is in a cut-off state, the voltage at the output terminal T1 of the write/read amplifier S1 remains at a low level regardless of the change in the emitter drive voltage VXt, and becomes ``0''.
The information ``'' is read out.

Note that X added to the first emitters of transistors Q1 and Q2
The size of the high level of address voltage ■X1 is the reference voltage EV
Collector voltage rEvc1 of transistor Q1 with respect to ref
is chosen so that the collector voltage c2 of transistor Q2 is high and the collector voltage c2 of transistor Q2 is low.

Furthermore, when writing to the memory cell M, when the transistors are in the selected state as in the case of reading, a signal at a level higher than the high level of the collector voltage of the memory cell or lower than the reference voltage EVref is applied to the bases of the transistors Q4 and Q6. ``1'' or ``0'' information is written.

In the above explanation, only the emitter drive voltage X1 is changed from a low level to a high level at the time of selection, but depending on the type of memory cell, not only the emitter drive voltage
It is known that a method of changing the collector power supply voltage aEvxo from a low level to a high level is also effective.

Needless to say, the present invention can also be applied to memory cells using this method.

Next, a case will be described in which the memory cells M and write/read amplifiers 81 and S2 shown in FIG. 1 are applied to a memory cell matrix having mXn rows.

In this case, for simplicity, m = n = 2 ? Let me explain the case.

FIG. 2 shows an example of this type of circuit.

In the four memory cells M11, M12, M2 1, and M22, the second emitter of each transistor constituting the flip-flop circuit is connected to two pairs of digit lines DLI.
, DL12, DL21 and DL2, respectively,
Each collector is connected to a collector power supply or a collector drive line (first word line) through a load resistor, to which electric currents X1o and X2o are applied, and further connected to a first emitter drive line (second word line). Voltage ■X11
, ■X21 can be added.

Current sources JILJ12 and J2LJ22 that supply the operating current ■R for reading or writing are connected to the digit line D, respectively.
Lt, DL12, DL2, DL22.

Transistor for detecting read information? Rtt j QR12
, QR21 t Each emitter of QR22 is connected to the above digit line, and each collector is connected to "0"
The digit lines on the side and 911111 side are connected to ground through respective collector resistors R8 and R9, and are led to the differential amplifier DIFA.

Write control signals ■w1, ■wo are transistors Qw1, ,
Qw1, QW2t > added to QW22.

In addition, the transistor QYt t Qy2 increases the potential of the unselected digit line pair in response to each digit line (Y line) selection signal ■Y1, ■Y2, thereby increasing the potential of all memory cells connected to that digit line pair. The second emitter of the transistor constituting the flip-flop circuit is cut off, and the current of the current source connected to the digit line pair is transmitted to the read information detection transistor QR,11t.
QR, 1t QR21 + Acts so as not to flow to QB2.

In the memory circuit shown in FIG. 2 above, if the power consumption due to the operating current of the memory is PT, then PT=2n・■R・
1■EE? The disadvantage is that the PT is large.

That is, power consumption increases in proportion to the number of memory cell rows n, which poses a major obstacle to increasing the density of memory cells by integrating them.

Also, the write control signal VWt vwo is the transistor Qw
n , QW12 5 QW21 , QW22 , and because the digit line potential fluctuates due to the digit line selection signal, the recovery time of the digit line potential becomes longer and the digit line potential changes. There are disadvantages in that the changes cause noise to the memory cells, and the required noise margin of the memory cells increases.

The present invention has been made to eliminate these drawbacks, and includes a set of current sources that supply operating current for a plurality of digit lines, and a multi-input switching circuit that switches the supply of operating current to each digit line. This reduces power consumption and prevents fluctuations in the potential of the digit line.

In FIG. 3, one set of current sources supplying the operating current R is set for a plurality of digit line pairs, and the supply of the operating current to each digit line is controlled by the digit line (Y line) selection signal R.
Transistors Qy 11 , Qy 12 JQY 21 5QY2 whose base potentials are controlled by Y1, ■Y2
, the reference transistor QR to which the reference voltage box ■ref2 is applied to its base, and the write signals ■wo, ■w1? Switching is performed by a multi-input current switching circuit formed by write control transistors QWo and Qw1 applied to the base.

Note that the low level of the write signal VWo tVWt is the reference voltage V.
By making it equal to ref2, the reference transistor Q
R can also be omitted.

In addition, the read signal detection transistor QRII t QR
It QR2t ,Q'R. 22 is the same as that in FIG. 2 above.

In such a configuration, the power consumption PT due to the memory operating current is PT=2 1R,X I VEE l ? given, and 1/n compared to that shown in Figure 2 above.
become.

That is, the power consumption is only for one column (actually, one memory cell) no matter how many columns n there are in the matrix made up of memory cells.

Another advantage of this configuration is that the number of write control transistors is reduced to 1/n of that in the case of FIG. 2.

Furthermore, since the emitters of the write control transistors Qwo and Qw1 do not drive the digit line directly, there is an advantage that the noise voltage appearing on the digit line is greatly reduced.

Next, the circuit shown in FIG. 3 is further improved to eliminate the risk of the potential of the digit line rising when it is not selected, thereby preventing memory cell malfunctions and the disadvantage of limiting the achievable cycle time. FIG. 4 shows an embodiment in which noise generation in the digit line is reduced.

In the figure, transistors QYt, QY12, QY2,
, QY22 are in the cut-off state, the potential of the corresponding digit line is approximately from the reference voltage EVref1 to QRII.
tQRIt QB, 21, QB, 2, the base-emitter forward voltage of each transistor ■EE, is subtracted by resistors Rl 1, Rl 2, R21, R22 between each digit line and the negative power supply ■EE This prevents the digit line potential from rising and noise from occurring.

For example, the transistor QRI, the resistor R11, and the negative power supply VER are formed by the transistor QR11, the resistor R11, and the negative power supply EE when the leftmost digit line in the figure is not selected and therefore the current ■R is not flowing. Since a current flows through the path, the voltage of this digit line is determined by Vref. is maintained.

In this way, by providing means for holding the voltage of the unselected digit line at a predetermined value, the rise in the potential of the unselected digit line and the generation of noise can be prevented.

In this way, the transistor QRt, the current path made up of the resistor R11 and the negative power source EE serve to maintain the voltage.

Moreover, this holding circuit is the transistor QR in this embodiment.
, 11 and a few other circuits, it is a simple circuit.

In particular, as in this embodiment, the read transistor Q
When Rt is used as it is as a voltage holding transistor, the voltage holding circuit becomes even simpler.

Further, FIG. 5 shows another embodiment.

In the figure, a transistor Qy for digit line selection is shown.
13, QY3 is a diode pair D whose cathodes are commonly connected
11 and D12, D21 and D22, the noise prevention resistors R11, R12, R21, used in FIG.
It functions to disconnect the current sources JO1 and JO2, which perform the same function as R22, from the selected digit line.

For example, when the digit line selection signal VYt is at a low level, both transistors QYII>QY12 are off, and the current ■R is not supplied to the pair of digit lines connected to the memory cells M11 and M21.

On the other hand, since the transistor QY13 is off, the base voltage of the transistor Q8,1 is equal to the negative voltage VSS, so the positive voltage E of the transistor pair QSII, QS12 is
Transistor Qs1 to which V ref is applied is turned on.

Similarly, among the transistor pair Qs,s,Qs 14,
Transistor Qs14 is turned on.

Therefore, resistor R3L. ．． l-transistor QS 12
, QRII, diode Dll, negative power supply J.

1, a current path consisting of a resistor R32, and a transistor QSt.
3j QR12, diode D12, negative power supply J.

A current IH flows in a distributed manner in a current path consisting of 1.

As a result, the potentials of the pair of unselected digit lines are maintained at a positive level determined by the reference voltage V ref1 applied to the bases of the transistors QRt 1 and Q12.

In this way, the current source Jo1, the diodes D11, D12,
Transistors QRIIt, QRt, etc. connect unselected digit lines to current source J.

By connecting it to 1, it functions to hold that voltage.

On the other hand, when the signal Y1 is at a high level, the transistor QY13 is turned on, and the diodes D11, ? The voltage of the cathode of No. 12 is lowered by the amount of the transistor's pace-emitter drop.

On the other hand, through the level shift circuit L1, the transistor QY1
1, QY1 is applied with a positive voltage obtained by level-shifting the signal Y1, these transistors are turned on, and current ■ flows.

Therefore, by appropriately selecting the amount of level shift,
The anode voltages of diodes D11 and D12 can be lower than their cathode voltages.

As a result, the diodes Dll and D12 are turned off, and the current source J is turned off.

1 is disconnected from these unselected digit lines.

Note that the current source J. The current ■H of 1 is the transistor QYt
It flows to the resistor R33 via a.

The level shift circuits Ll and L2 can be omitted in some cases as described below.

That is, transistor pair QY 11 and QY12 j Q
By driving the commonly connected bases of Y2 and QY2 by the commonly connected cathodes of the diode pairs D11 and D12, D21 and D22, a level shift circuit L is applied to the transistor QYta j QY23.
It can also have the function of 1 t L 2.

In FIG. 5 above, the reference transistor QRutQRt
Transistors QsH and Q312 are connected to the collectors of t QR,21 and QB2, respectively. t QS13 and QS14
j A current switching circuit consisting of QS21 and Qs22, Qs23 and QS24 is provided, and the current flowing to the resistors R31 and R32 for forming an OR circuit for the read signal is made to flow only from the selected digit line.

The control signal for this current switching circuit is the current source J
The voltage drop that occurs across resistors R33 and R34 due to the currents H of OI and JO2 is used.

Next, the readout amplifier will be explained.

Conventionally, a differential amplifier is used as the readout amplifier shown in FIG. This is usually accomplished using a strobe pulse.

On the other hand, in the present invention, this can be done very easily by adding an appropriate potential difference to the voltage (2Bt t VB2M) applied to one end of the resistors R31 and R32.

FIG. 6 shows a differential amplifier to which this is applied and its input section.

In this figure, by providing a resistor R35, an effect equivalent to the case where the power supply voltages 1B1 and 2B2 in FIG. 5 are made different is obtained.

This makes it possible to stabilize the operation of the transistors QAI + QA2 constituting the differential amplifier, keep the output at a low level when there is no input, and set it to a high level only when the readout output is "1'".

The circuit shown in FIG. 5 includes a transistor QY13, diodes Dll and D12, and a current source J.

A voltage holding circuit is formed by the diodes D11 and D11, etc., but this circuit is substantially different from the circuit shown in FIG.
Although D12 is additionally required, as already mentioned, there is an advantage that the read amplifier can be controlled using the collector current of this transistor QY13.

As described in detail above, according to the present invention, it is possible to reduce the number of current sources for supplying read current or write current to a current switching type memory device, thereby significantly reducing power consumption and reducing potential fluctuations of digit lines. The noise caused by this is reduced and the read amplifier operates stably, which brings great advantages as a semiconductor memory device.

Note that although the power consumption is saved by the invention of the present application, if the power consumption is allowed to be the same value as the conventional one, the current capacity of the current source of the present application can be increased.

In other words, it is equivalent to placing the individual current sources connected to each digit line in one place, ? This has the great effect of increasing speed without increasing power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a current switching type Marchemitsuta memory cell and a read/write circuit, FIG. 2 is a memory matrix circuit diagram using the memory cell shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. 4 to 6 are circuit diagrams of the portion related to power consumption reduction, and FIGS. 4 to 6 are circuit diagrams of embodiments of the present invention. C1...Power supply terminal, E1...Emic drive terminal, E2, E3...Power supply terminal, DI
FA・・・Differential amplifier, JLJ2, JILJ12
, J2LJ22... Current source, Ll, L2...
...Level shift circuit, M, Ml 1 , M1 2
, M2 1 , M22... memory cell, Q1,
Q2...Memory cell transistor, QR...
...Reference transistor, QR tt ~ QR13 t
QR21 to QR23... Read signal detection transistors, Qs11 to Qs14, QS2 to QS24
・・・・・・Transistor for switching readout circuit Qwo
+ Qw. t Qwtt , QW12 > QW2
ttQW2J...Write control transistor,
QYtt~QY13, QY2~QY23... Digit line selection transistor, S1, S2...
・Write/read amplifier, T1, T2... Output terminal, Vref, Vrefo, ■ref1, 'V're
f2゜゜゜゜゜゜Reference voltage・■EEtsu■Bl, ■B2,
■SS: Power supply voltage, ■Y1, ■Y2... Digit line pair selection signal, ■wo, ■w1... Write control signal, R11, R12, R2 1, R22...
...Noise prevention resistor.

Claims (1)

[Claims] 1. A memory cell matrix consisting of a plurality of word lines, a plurality of digit lines, and memory cells provided at the intersections of each word line and each digit line; A circuit for reading or writing to a memory cell, a current source provided in common to the plurality of digit lines, a switch means for selectively connecting the current source to a selected digit line, and each digit line. A storage device in which each digit is provided with an electric ball holding circuit for holding the voltage at a predetermined value when the digit line is not selected. 2. Each of the voltage holding circuits consists of a transistor whose emitter is connected to the corresponding digit line, and a current path connected to the emitter for flowing a current different from the current of the current source, and when not selected. 2. The memory device according to item 1, wherein the memory device holds an electric ball of a digit line corresponding to a voltage determined by the voltage applied to the base of the transistor.