JPS63876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device suitable for a bipolar type high-speed semiconductor memory circuit.

[Background of the invention]

A memory cell having a plurality of emitters, that is, a combination of two multi-emitter transistors, is suitable as a memory cell for a large-capacity semiconductor storage device because it occupies a small area when integrated into an integrated circuit. An example of a memory cell using the above is shown in FIG.

In the figure, a memory cell M includes multi-emitter transistors Q1 and Q2 having two emitters.
The collectors of the transistors Q1 and Q2 pass through load resistors R1 and R2, respectively, are connected in common, and are connected to the power supply terminal C1 through a resistor R3.

Further, the collectors of the transistors Q1 and Q2 are each cross-connected to the base of the other, and the first emitters of the transistors Q1 and Q2 are commonly connected to the emitter drive terminal E1 for memory cell selection, and the second emitters of the transistors Q1 and Q2 are connected to each other in common to the emitter drive terminal E1, which will be described later. It is connected to amplifiers S1 and S2 for writing and reading.

A flip-flop circuit as one memory cell is thus formed. Note that transistor Q
Although the second emitters of transistors Q1 and Q2 are commonly connected to the second emitters of transistors constituting a plurality of other memory cells, they are omitted in FIG. 1 for the sake of simplicity.

The write/read amplifiers S1 and S2 are transistors Q3, Q4 and Q, respectively, which constitute a differential amplifier.
Consisting of 5, Q6, Q3 and Q4 and Q5 and Q6
The respective emitters of are commonly connected to the second emitters of the transistors Q1 and Q2, respectively, and are connected to the power supply terminals E2 and E via resistors R5 and R7 that define the read current or write current of the memory cell M.
3, and the collectors of transistors Q3 and Q5 are connected to output terminals T1 and T2, respectively, and grounded via resistors R4 and R6. In addition, the reference voltage is applied to the bases of transistors Q3 and Q5.
V _ref is applied, and input signals V _{W0 and W1} for information writing are applied to the bases of transistors Q4 and Q6.

Next, its operation will be explained. The memory cell M is selected by keeping the voltage V _X0 of the collector power supply terminal C1 constant.
This is done by setting the voltage _VX1 of the emitter drive terminal E1 to a low level when not selected and to a high level when selected. In this case, the transistor Q
It is assumed that Q1 is in the cutoff state and Q2 is in the conductive state, and the respective collector voltages are V _C1 and V _C2 .

Memory cell M is in a non-selected state, that is, terminal E1
When the emitter drive voltage _VX1 applied to the transistor Q2 is at a low level, a current _IST always flows through the first emitter of the transistor Q2, but no current flows through the second emitter. Write and read amplifier S
The current I _R flowing through the emitter resistor R7 of No. 2 flows through the resistor R7 rather than the transistor Q5, so the output voltage V _put of the transistor Q5 is V _put = V _CC −α・R6・I _R where α: transistor base common current amplification Only a low voltage indicated by the rate appears. Note that the operating currents flowing through the resistors R5 and R7 are set to the same current value I _R .

Next, the memory cell M is in the selected state, that is, the terminal E1
When the emitter drive _{voltage V}
Therefore, the current flowing through the collector resistor R6 decreases, the voltage at the output terminal T2 increases, and becomes "1".
The following information is read out. Note that since the transistor Q1 is in the cut-off state, the voltage at the output terminal _T1 of the write/read amplifier S1 remains at a low level regardless of changes in the emitter drive voltage _VX1 , and information of "0" is read out.

Note that the magnitude of the high level _of the _{X address} voltage _V are selected as such.

Also, when writing to the memory cell M, when in the selected state, the transistors Q4 and
Information of "1" or "0" is written by applying a signal at a level higher than the high level of the collector voltage of the memory cell or at a level lower than the reference voltage V _ref to the base of Q6.

Note that in the above explanation, the emitter drive voltage is
Although we have assumed that _{only V} It is known. Needless to say, the present invention can also be applied to memory cells using this method.

Next, a case will be described in which the memory cell M and the write/read amplifiers S1 and S2 shown in FIG. 1 are applied to a memory cell matrix in which m×n rows are provided. In this case, for simplicity, the case where m=n=2 will be explained.

FIG. 2 shows an example of this type of circuit. M11,
In the four memory cells M12, M21, and M22, the second emitter of each transistor constituting the flip-flop circuit is connected to two pairs of digit lines.
D _L11 , D _L12 , D _L21 and D _L22 are respectively connected, and each collector is connected to the collector power supply or collector drive line (first word line) through a load resistor.
It is connected to the first emitter drive line (second word line) to which voltages V _X10 and V _X20 are applied, and is further connected to the first emitter drive line (second word line) to which voltages V _X11 and V _X21 are applied.

Current sources J11, J12, J21 and J22 supplying operating current I _R for reading or writing are connected to digit lines D _L11 , D _L12 , D _L21 and D _L22 , respectively. Read information detection transistor Q _R11 ,
The emitters of Q _R12 , Q _R21 , and Q _R22 are each connected to the above digit line, and each collector is connected to the digit line on the "0" side and the "1" side through the respective collector resistors R8 and R9. It is grounded and guided to the differential amplifier DIFA.

Write control signals V _W1 , V _W0 are transmitted through transistors Q _W11 ,
Added to Q _W12 , Q _W21 , and Q _W22 . In addition, transistors Q _Y1 and Q _Y2 increase the potential of the unselected digit line pair in response to the respective digit line (Y line) selection signals V _Y1 and V _Y2 , so that all memory cells connected to that digit line pair are The second emitter of the transistor constituting the flip-flop circuit inside is cut off, and the current of the current source connected to the digit line pair does not flow to the read information detection transistors Q _R11 , Q _R12 , Q _R21 , Q _R22 . It works like this.

In the memory circuit shown in FIG. 2, where P _T is the power consumption due to the operating current of the memory, P _T =2n· _IR ·|V _EE |, and the disadvantage is that P _T is large. That is, power consumption increases in proportion to the number of memory cell rows n, which poses a major obstacle to increasing the density of memory cells by integrating them. Also, write control signals V _W1 , V _W0
is applied directly to the digit line through transistors Q _W11 , Q _W12 , Q _W21 , and Q _W22 and because the digit line potential fluctuates due to the digit line selection signal, the recovery time of the digit line voltage becomes longer. However, there are disadvantages in that changes in the digit line potential cause noise to the memory cells, and that the required noise margin of the memory cells becomes larger.

[Purpose and outline of the invention]

The present invention has been made to eliminate these drawbacks, and consists of a set of current sources for supplying operating current for a plurality of digit lines, and supply of operating current to each digit line by a multi-input switching circuit. This reduces power consumption and prevents fluctuations in the potential of the digit line.

[Embodiments of the invention]

In FIG. 3, one set of current sources for supplying the operating current I _R is provided for a plurality of digit line pairs, and the supply of operating current to each digit line is controlled by digit line (Y line) selection signals V _Y1 and V _Y2 . Transistors Q _Y11 , Q _Y12 , Q _{Y2 1} , Q _Y22 whose base potentials are controlled by
, a reference transistor Q _R to which a reference voltage V _ref2 is applied to its base, and write control transistors Q _W0 and Q _W1 to which write signals V _W0 and V _W1 are applied to their bases.
Switching is performed by a multi-input current switching circuit formed by. Note that the reference transistor _QR can be omitted by making the low level of the write signals V _W0 and V _W1 equal to the reference voltage V _ref2 .
In addition, read signal detection transistors Q _R11 , Q _R12 ,
Q _R21 and Q _R22 are the same as those in FIG. 2 above.

In such a configuration, the power consumption P _T due to the memory operating current is given by P _T = 21 _R × |V _EE |, which is n compared to that shown in Fig. 2 above.
It becomes 1/1. That is, the power consumption is only for one column (actually, one memory cell) no matter how many columns n there are in the matrix made up of memory cells. Another advantage of this configuration is that the number of write control transistors is reduced to 1/n of that in the case of FIG. 2.

Furthermore, write control transistor Q _W0 ,
Since the digit line is not directly driven by the emitter of Q _W1 , there is an advantage that the noise voltage appearing on the digit line is extremely reduced.

By the way, when a set of current sources for supplying operating voltage is used for a plurality of digit lines, and the supply of operating current to each digit line is switched,
In general, unselected digit lines are electrically floated and their potential fluctuates due to noise or the like, resulting in malfunctions of memory cells and limitations in achievable cycle time. Therefore, it is necessary to provide a circuit that holds the potential of unselected digit lines.

In the embodiment shown in FIG. 3, this voltage holding circuit is formed by a readout transistor to which a reference voltage is applied to the base.
It consists of Q _R11 , Q _R12 , Q _R21 , and Q _R22 . In the figure, transistors Q _Y11 , Q _Y12 , Q _{Y2 1} , Q _Y22
When is in the cut-off state, the potential of the corresponding digit line approximately changes from the reference voltage V _ref1 to Q _R11 , Q _R12 ,
It is clamped so that it does not fall below the value obtained by subtracting the base-emitter forward voltage V _BE of each transistor Q _R21 and Q _R22 .

In the embodiment shown in FIG. 3, the leakage current from the collectors of the transistors Q _Y11 , Q _Y12 , Q _{Y2 1} , and Q _Y22 prevents the potential of the digit line from increasing in the positive direction when not selected. The voltage holding power against positive direction noise cannot be said to be sufficient.

Further, the transistors θ _Y1 and θ _Y2 shown in FIG. 2 can also be expected to have the same effect as described above.

Next, the circuit shown in FIG. 3 is further improved to eliminate the risk of the potential of the digit line rising when not selected, thereby preventing malfunction of the memory cell and the disadvantage of limiting the achievable cycle time. FIG. 4 shows an embodiment in which noise generation in the digit line is reduced.

In the figure, transistors Q _Y11 , Q _Y12 , Q _Y21 ,
When Q _Y22 is in the cut-off state, the potential of the corresponding digit line changes approximately from the reference voltage V _ref1 to Q _R11 ,
The base of each transistor Q _R12 , Q _R21 , Q _R22
By connecting resistors R11, R12, R21, and R22 to a value that subtracts the emitter forward voltage _VBE between each digit line and the negative power supply _VEE , a rise in the digit line potential and generation of noise are prevented. It is something.

For example, when the leftmost digit _line in the diagram is not selected and therefore no current I _R flows, the transistor Q _R11 , the resistor _R11 , and the negative power supply V _EEE
Since current flows through the path formed by Vref1, the voltage on this digit line is held at a voltage determined by _Vref1 . In this manner, by providing means for holding the voltage of the unselected digit line at a predetermined value, rise in the potential of the unselected digit line and generation of noise can be prevented. Like this transistor Q _R11
The current path consisting of the resistor R11 and the negative power supply _VEE serves to maintain the voltage. Furthermore, this holding circuit is a simple circuit in this embodiment since it consists of only the transistor Q _R11 and a few other circuits. In particular, when the read transistor Q _R11 is used as it is as a voltage holding transistor as in this embodiment, the voltage holding circuit becomes even simpler.

Furthermore, as is clear from the above description, the role of the voltage holding circuit of the present invention is to hold the potential of the digit line when it is not selected.
The operating margin of the memory cell can be further improved by setting the base voltage of the voltage holding transistor when not selected to different values when the digit line is selected and when the digit line is not selected.

Further, FIG. 5 shows another embodiment. In the figure, transistors Q _Y13 for digit line selection,
Q _Y23 is a diode pair D1 whose cathodes are connected in common.
1 and D12, D21 and D22, the noise prevention resistors R11 and R1 used in FIG.
2, R21, and R22 to separate the current sources J01 and J02 from the selected digit line.

For example, when the digit line selection signal V _Y1 is at a low level, both the transistors Q _Y11 and Q _Y12 are off, and the current I _R is not supplied to the pair of digit lines connected to the memory cells M11 and M21. On the other hand, since the transistor Q _Y13 is off, _the base voltage of _{the transistor Q S11 is equal} to _the positive voltage V _SS . Q _S12
is off, and transistor Q _S11 is on. Similarly, of the transistor pair Q _S13 and Q _S14 , the transistor
Q _S14 turns on. Therefore, the transistor
Current flows through a current path consisting of Q _S12 , Q _R11 , diode D11, and negative power supply J ₀₁ and a current path consisting of transistors Q _S14 , Q _R12 , diode D12, and negative power supply J ₀₁ .
_IH flows in a dispersed manner. As a result, the potentials of the above pair of unselected digit lines are the same as those of the transistors Q _R11 and
It is held at a voltage determined by the reference voltage V _ref1 applied to the base of Q _R12 . Thus the current source J ₀₁ ,
Diodes D11, D12, transistor Q _R11 ,
Q _R12 and the like serve to maintain the voltage of unselected digit lines by connecting them to the current source _J01 .

On the other hand, when the signal V _Y1 is at a high level, the transistor Q _Y13 is turned on and the diodes D11 and D
The voltage at the cathode of 12 is lowered by the base-emitter drop of the transistor. On the other hand, the transistors Q _Y11 and Q _Y12 are connected via the level shift circuit L1.
A level-shifted voltage of signal V _Y1 is applied to
These transistors turn on and current I _R flows. Therefore, by appropriately selecting the amount of level shift, the anode voltages of the diodes D11 and D12 can be made lower than their cathode voltages.
As a result, diodes D11 and D12 are turned off and current source _J01 is disconnected from these selected digit lines. In addition, the current I _H of current source J ₀₁
will flow to the resistor R33 via the transistor Q _Y13 .

The level shift circuits L1 and L2 can be omitted in some cases as described below. In other words, the commonly connected bases of the transistor pairs Q _Y11 and Q _Y12 and Q _Y21 and Q _Y22 are connected to the diode pair D.
Level shift circuit _{L1 ,}
It can also function as L2.

In Fig. 5 above, the reference transistor Q _R11 ,
Transistors Q _S11 and Q _S12 , Q _S13 and Q _S14 , Q _S21 and Q _S22 are connected to the collectors of Q _R12 , Q _R21 , Q _R22 , respectively.
A current switching circuit consisting of Q _S23 and Q _S24 is provided, and the current flowing through the resistors R31 and R32 for forming an OR circuit for read signals is made to flow only from the selected digit line. As a control signal for this current switching circuit, a voltage drop generated across resistors R33 and R34 due to the current _IH of the current sources J01 and J02 is used.

Next, the readout amplifier will be explained. 5th above
Conventionally, a differential amplifier is used as the readout amplifier shown in the figure, but it is possible to keep its output at a low level at all times and set it to a high level only when the readout output is "1", and to take a wired OR with the emitter of the output emitter follower. This is typically achieved using strobe pulses. On the other hand, in the present invention, this is done very simply by adding an appropriate potential difference to the voltages V _B1 and V _B2 applied to one ends of the resistors R31 and R32.

FIG. 6 shows a differential amplifier to which this is applied and its input section. In the same figure, by providing the resistor R35, the power supply voltages V _B1 and V _B2 in FIG.
This has the same effect as when there is a difference between the two. This stabilizes the operation of transistors Q _A1 and Q _A2 that constitute the differential amplifier,
The output can be kept at a low level when there is no input, and can be set to a high level only when the readout output is "1".

In the circuit shown in FIG. 5, a voltage holding circuit is formed by the transistor Q _Y13 , diodes D11, D12, current source _J01 , etc., but compared to the circuit shown in FIG. D11,
Although D12 is additionally required, as already mentioned, there is an advantage in that the readout amplifier can be controlled using a current flowing through the collector of this transistor _QY13 .

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to reduce the number of current sources for supplying read current or write current to a current switching type memory device, thereby significantly reducing power consumption and reducing potential fluctuations of the digit line. The noise caused by this is reduced and the read amplifier operates stably, which brings great advantages as a semiconductor memory device.
Note that although the power consumption is saved by the invention of the present application, if the power consumption is allowed to be the same value as the conventional one, the current capacity of the current source of the present application can be increased.
In other words, this is equivalent to concentrating the individual current sources connected to each digit line in one place, which has the great effect of increasing speed without increasing power consumption. It turns out.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a current-switching multi-emitter memory cell and a read/write circuit, FIG. 2 is a memory matrix circuit diagram using the memory cell shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. 4 to 6 are circuit diagrams of portions related to power consumption reduction, and FIGS. 4 to 6 are circuit diagrams of embodiments of the present invention. C1...power supply terminal, E1...emitter drive terminal, E2, E3...power supply terminal, DIFA...differential amplifier, J1, J2, J11, J12, J21, J
22...Current source, L1, L2...Level shift circuit, M, M11, M12, M21, M22...Memory cell, Q1, Q2...Memory cell transistor, Q _R ...Reference transistor, Q _R11 ~Q _R13 ,
Q _R21 ~ Q _R23 ... Read signal detection transistor,
Q _S11 ~ Q _S14 , Q _S21 ~ _{Q S24} ... Readout circuit switching transistor, Q _W0 , Q _W1 , Q _W11 , Q _W12 , Q _W21 ,
Q _W22 ...Write control transistor, Q _Y11 ~
Q _Y13 , Q _Y21 ~ _{Q Y23} ... Digit line selection transistor, S1, S2 ... Write and read amplifier, T
1, T2...Output terminal, V _ref , V _ref0 , V _ref1 ,
V _ref2 ... Reference voltage, V _EE , V _B1 , V _B2 , V _SS : Power supply voltage, V _Y1 , V _Y2 ... Digit line pair selection signal,
V _W0 , V _W1 ...Write control signal, R11, R12,
R21, R22...Resistors for noise prevention.

Claims (1)

[Scope of Claims] 1. A memory cell matrix consisting of a plurality of word lines, a plurality of digit lines, and memory cells provided at the intersections of each word line and each digit line, and a memory cell selected via the digit lines. A circuit for reading or writing cells, a current source commonly provided to the plurality of digit lines, a switch means for selectively connecting the current source to the digit line to be selected, and a current source provided in common to the plurality of digit lines; A storage device in which each digit is provided with a voltage holding circuit for holding the voltage at a predetermined value when the digit line is not selected, wherein the switching means includes a transistor to which a digit line selection signal is input;
1. A memory device comprising a multi-input current switching circuit including a transistor to which a write signal is input. 2. A plurality of memory cells each consisting of a plurality of word lines and two multi-emitter transistors each having a collector load and forming a flip-flop by cross-connection are formed into a pair, and when one is at a high potential, A memory matrix comprising a plurality of memory cell rows arranged on two digit lines, the other of which is at a low potential, and one emitter of each multi-emitter transistor of the memory cell is connected to each of the digit lines. a circuit for reading or writing to the selected memory cell via the digit line; a current source commonly provided to the plurality of digit lines; and a circuit for selectively applying the current source to the digit line to be selected. a voltage holding circuit having a configuration in which the emitter of at least one transistor is connected to the digit line in order to maintain the voltage of each digit line at a predetermined value when the digit line is not selected; A storage device characterized in that it is provided on the digit line.