JPS5847860B2 - Hand tie souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved wiring between elements.

Conventionally, as a semiconductor device using polycrystalline Si as a wiring member, for example, Si gate complementary MIS (Metal-
Insulator - Semiconductor
r) is known.

That is, as shown in FIG. 1, a first drain 101, a first source 102, an Al wiring 103 from the first drain, and a first gate electrode 104 made of p-type polycrystalline silicon. A p-channel transistor consisting of a first source 102, an Ad wiring 105 common to a second drain 106, a second drain 106, a second source 107, and an A7 wiring from the second source. 108 and
Second gate electrode 10 made of n-type polycrystalline silicon
9, and an Al wiring 105 connected to the second drain 106 common to the first source 102. The electrodes 109 are connected by a connecting member aluminum 112 through respective contact windows.

A complementary MIS inverter is constructed as described above.

However, while the source and drain can be formed in self-alignment, as mentioned above, a connection member between the polycrystalline silicon gate electrode members is required, and the large area occupied by this or the area occupied by the connection part is difficult to integrate in semiconductor integrated circuits, etc. It becomes an obstacle to development.

In addition, since Al is used as a connecting member, it is difficult to multilayer device wiring. The present inventors have succeeded in replacing conventional impurity-doped polycrystalline silicon by using a wiring member made of semiconductor and metal as an electrode member. It is possible to lower the resistivity by 1 to 3 orders of magnitude compared to
Moreover, it was discovered that high integration is possible. The present invention was made in view of the above points, and it is possible to improve the degree of integration by directly connecting with a material made of metal silicide or a metal-semiconductor co-product. The present invention provides a semiconductor device according to the present invention.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

On a substrate, for example, a sapphire substrate 1, a semiconductor layer, for example, a Si layer 2n type surface direction (100) is formed by thermal decomposition of silane or the like.
A specific resistance of, for example, 3.58.

Next, C V D Si 02 is applied to a thickness of 3000 mm, and this Si 02 is patterned by photo-etching. Using this as a mask, the Si layer 2 is pattern-etched using hydrazine at 70° C.
a first island-shaped Si3 on which a channel transistor is formed;
Second island-shaped Si4 where an n-channel transistor is formed
form.

Next, after removing the Si02 for the mask, the Si02 is removed at a temperature of, for example, 1050'C in a wet oxygen atmosphere.
The layer 2 is oxidized to form a thermal oxide film 5 having a thickness of 1200 nm.

Next, for example, the first island-shaped Si3 is coated with a resist 6, and at an accelerating voltage of, for example, 80 KV, for example, boron is 7×
Ions are implanted at a rate of about 10''/era to change the device shape of some portions of the second island-shaped Si4 to p-type.

At this time, the Si4 surface concentration was 7×10 15 /air.

After removing the resist 6, a molybdenum (Mo) layer 7 having a thickness of, for example, 1000 layers is formed by vacuum evaporation or the like.

Then, using e.g. pyrolysis of silane, the temperature e.g.
A boron-doped polycrystalline Si layer 8 is deposited at a temperature of, for example, 3000°C.

From this point, Mo-silicide is formed.

Next, 4000 layers of CVD Si02 are formed, and pattern etching is performed using a conventional method to form a mask.

Using this Si02 as a mask, the Mo-silicide is pattern-etched leaving desired portions (gate electrode portion and wiring portion) to form the first wiring member 9.

Next, this mask Si02 is removed to a thickness of, for example, 100 mm.
00 molybdenum 10 is formed by vapor deposition or the like.

Next, polycrystalline Sil1 doped with boron at, for example, 600°C by thermal decomposition of silane is deposited to a thickness of, for example, 2000°C.
People settle down.

At this time, Mo-silicide is formed.

Next, this Mo-silicide is patterned in the same manner as described above to form the second wiring member 12.

As an etching solution for silicide, HF'HNO
s' CH3 COOH: I 2 = 0.
24(l): 0. 1(l): 0. 7 5 (
#): 0. 2(g) was used.

At this time, the first wiring member 9 and the second wiring member 1
2 is as shown in FIG.

Gate wiring is performed by the above method.

Next, by the CVD method, the thickness of Si021, for example 4000, is
form 3.

Next, using ammonium fufluoride, the CVD Si021
CVDSiO 21 of the first island-shaped Si 3 portion where the p-channel transistor is formed.
3 is removed and C covering the second island-like Si portion 4 is removed.
Leave VD S i021 3.

Next, diffuse boron for 10 minutes at a temperature of, for example, 1050°C.
The source 14 and drain 15 regions of the p-channel transistor are formed.

Next, the entire surface was coated with SiO216 with a thickness of 4,000 people using the CVD method.
formal precepts.

Next, the p-channel transistor section is covered with Si02
The Si0216 covering the second island-shaped Sia portion is removed, leaving 16.

Next, phosphorus is diffused at 1000° C. for 10 minutes using, for example, POC73 to form the source 17 and drain 18 regions of the n-channel transistor.

At this time, since the silicide in the wiring part is an alloy, p
- There is no possibility of forming an n-junction.

Next, CVD SiO2 with a thickness of 1.2 μm is formed on the entire surface.

Next, after forming a window for electrode contact, Mo-silicide is formed in the same manner as described above and patterned to form the source electrode 21 of the p-channel transistor and the p-silicide.
A wiring 20 connecting the drain of the channel transistor and the source of the n-channel transistor and a drain electrode 22 of the n-channel transistor are formed.

When the complementary MIS inverter thus formed is viewed from above, it is as shown in FIG.

In the above embodiment, a case was shown in which two different electrode members were directly connected, but it is also possible to connect three or more electrode members, at least two of which are directly connected to each other.

In the above embodiment, Mo-silicide was used as the wiring member, but other metal silicide or Ge
-Au, Al-Si, Ni-Si, and other eutectics can be used in any combination (for example, wiring members of different compositions can be combined depending on the purpose).

In the above embodiment, the wiring member silicide is formed by a thermal reaction between the vapor-deposited metal and the semiconductor, but the manufacturing method is not limited to this. As explained above, according to the present invention, unnecessary connecting members are eliminated. This is particularly effective in integrating semiconductor integrated circuits, etc., since the wiring members can be directly connected to each other without using.

Furthermore, when polycrystalline silicon is used for the gate as in the prior art, conductivity type impurities are also introduced into the gate when forming the source and drain, and the threshold value VTR of the transistor fluctuates.

For example, in a complementary MIS inverter, if VTH were to move to a shallower side, a leak current would occur from a transistor that is OFF, and the advantage of low power consumption would be lost.

Conversely, when VTH moves deeper, the channel current during operation decreases, which is equivalent to a decrease in conductance fJm, and the characteristic of exhibiting high speed with low power consumption is lost. Put it away.

Also, VDD=5V sVTH (threshold value of N-channel transistor)=+o. s v , VT=-〇. When optimally designed at 8V, a single conductivity type inverter has an operating margin of about 1.5V, whereas a complementary MIS inverter has a high operating margin of 2.5V.

However, when the above-mentioned VTH fluctuation occurs, the operating margin is impaired, and the characteristic of the high operating margin of the complementary MIS inverter is impaired.

If the dose is lowered to prevent VTH fluctuations,
The sheet resistance ρS of the source and drain decreases.

On the other hand, in the present invention, the gate material of the complementary MIS inverter is a metal silicide or a metal-semiconductor composite layer, so even if conductivity type impurities are mixed, the V
There is little variation in TR.

Therefore, complementary MI can be performed without considering complicated process conditions.
Another feature is that an S inverter can be obtained.

Furthermore, multilayering of element wiring becomes easy.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional complementary MIS inverter, Figure 2
The figure is a sectional view of an element manufacturing process for explaining one embodiment of the present invention, FIG. 3 is a schematic diagram of an MIS inverter manufactured by the process shown in FIG. 2, and FIG. FIG. 2 is a diagram for supplementary explanation. In the figure, 1... sapphire substrate, 3, 4...
...Si, 14, 17... Source, 15
, 18... drain, 9... first wiring member, 12... second wiring member.

Claims (1)

[Claims] 1 P-channel and N-channel MI where the source and drain are self-aligned with the gate electrode on the substrate
S} transistors are provided, and the gate electrodes and their extensions of the P-channel and N-channel MIS transistors are respectively constructed of metal silicide or metal-semiconductor co-product layers, and the layers are connected to each other without using connection wiring. A semiconductor device characterized by being connected to form an inverter.