JPS5847864B2 - field effect transistor - Google Patents

Description

[Detailed description of the invention] The present invention relates to field effect transistors.

There are conventional field effect transistors of junction type and insulated gate type, but they usually function as switching elements but not as memory elements.

However, there are special insulated gate field effect transistors that have the functions of both a switching element and a memory element; Normally, it was not possible to use both functions together.

For this reason, in the case of conventional field effect transistors, when using them to configure a memory circuit that requires both the function of a memory element and the function of a switching element, the field effect transistor must be used at least two times. Individually required,
Therefore, when constructing a memory circuit using such field effect transistors, there are certain limits to how small the memory circuit can be made to be, and it is also difficult to increase the speed at which information can be written to or read from the memory circuit. This method has disadvantages such as a certain limit in reducing the voltage required to write or rewrite information to a memory circuit.

Therefore, the present invention aims to propose a novel field effect transistor that does not have the above-mentioned drawbacks and is therefore suitable for use in configuring a memory circuit, as will become clear from the detailed description below with reference to the drawings. Will.

FIG. 1 shows a first embodiment of a field effect transistor according to the present invention, which has a P-type semiconductor layer 1 made of, for example, a P-type silicon substrate. type semiconductor regions 3 and 4 with a semiconductor layer 1 between them.
In order to form the semiconductor region 5 as a channel region, the semiconductor region 5 is formed as a source region and a drain region, respectively, by known means such as N-type impurity diffusion treatment and N-type impurity ion implantation treatment.

Further, a charge storage insulating layer 6 and a non-charge storage insulating layer I are juxtaposed on the main surface 2 side of the semiconductor region 5 serving as a channel region, and a charge storage insulating layer 6 and a non-charge storage insulating layer I are arranged side by side. Conductive layers 8 and 9 are provided on the conductive insulating layer T, respectively.
It is arranged as a gate electrode.

In this case, when a voltage is applied between the semiconductor region 5 and the conductive layer 8 with the conductive layer 8 side being negative, the charge accumulating insulating layer 6 When polarization is applied such that the interface side with the semiconductor region 5 is negative and the voltage that is positive on the conductive layer 8 side, the interface side with the semiconductor region 5 is negative and the interface side with the conductive layer 8 is positive. In order to have the property of accumulating charges on the interface side with the semiconductor region 5 and on the interface side with the conductive layer 8 in such a manner that polarization can be obtained, the veloping force of barium titanate, lead titanium zirconate, etc. is used. It has a shape including a ferroelectric material such as a metal salt type, a Rothsiel salt type, or a potassium phosphate type, and extends over a region 5a that is a half of the semiconductor region 5 on the semiconductor region 3 side.

Further, the non-charge accumulating insulating layer 7 includes the semiconductor region 5 and the conductive layer 9.
The other half of the semiconductor region 5 on the semiconductor region 4 side is formed of an insulator such as silicon oxide so that it does not have the property of substantially accumulating electric charge even if a voltage is applied therebetween. The charge storage insulating layer 6 is connected to and extends on the charge storage insulating layer 5b.

Further, a conductive layer 8 disposed on the charge accumulating insulating layer 6 is made of a conductive material such as polycrystalline silicon or metal, and is covered with an insulating layer 12, which will be described later, together with the charge accumulating insulating layer 6. .

Furthermore, the conductive layer 9 disposed on the non-charge accumulating insulating layer 7 is also formed of a conductive material such as polycrystalline silicon, metal, etc., and extends over the area of the insulating layer 12 which can extend onto the conductive layer 8. are doing.

Further, a window is provided on the main surface 2 of the semiconductor layer 1, covering the charge storage insulating layer 6 and the conductive layer 8, extending in connection with the non-charge storage insulating layer 7, and allowing the semiconductor regions 3 and 4 to be exposed to the outside. An insulating layer 1 made of silicon oxide, for example, in which holes 10 and 1.1 are formed.
2 is formed, and an insulating layer 12 is formed in the semiconductor regions 3 and 4.
Conductive layers 13 and 14 made of, for example, metal and extending to
They pass through windows 10 and 11, respectively, and are connected as a source electrode to a wiring layer and a drain electrode to a wiring layer.

The above is the structure of the first embodiment of the field effect transistor according to the present invention. Between 9 and 9, a conductive layer 9 generally represented by ■G
By applying a voltage above a certain value with the side positive,
An N-type inversion layer (referred to as a second inversion layer) is formed on the surface side of the insulating layer 7 side of the region 5b under the insulating layer 7 of the semiconductor region 5.

Further, by applying a voltage generally represented by V'G between the conductive layer 13 and the conductive layer 8 serving as the first gate electrode, the voltage v'G is positive with the conductive layer 13 side being positive. In this embodiment, polarization is formed such that the interface side of the charge accumulating insulating layer 6 with the semiconductor region 5 is positive or negative, and the interface side with the conductive layer 8 is negative or positive. charge is accumulated.

This relationship shows that the voltage v'G is plotted on the horizontal axis, and the voltage v'G is plotted on the vertical axis, with the second inversion layer lying on the surface side of the region 5a as described above, and the semiconductor region 3 serving as the source region and the voltage v'G serving as the drain region. As shown in FIG. 2, which shows the current ID flowing between the semiconductor regions 4, when the voltage V'G is a positive value larger than 4, the insulating layer 6 is at the interface with the semiconductor region 5. A saturated polarization in which the side is positive is obtained, and a first inversion layer connected to the above-mentioned second inversion layer is obtained in the region 5a under the insulating layer 6 of the semiconductor region 5, thereby causing the current ID to become saturated. Although the value of the state is obtained, the voltage v′G from such a state can be
A negative value smaller than 4 ■ If a value smaller than 2, the polarization that corrects the interface side of the insulating layer 6 with the region 5 becomes smaller than the saturated state, and a negative value ■ A value smaller than 1. In this case, a saturated polarization is obtained in which the interface side with the region 5 is negative in the insulating layer 6, and the above-mentioned first inversion layer is not obtained in the region 5a, so that the current ID is obtained with a value of zero. , and from this state, if the value of voltage V'G is made larger than ■1 and a value that is smaller than the positive value v3, the polarization that makes the interface side with region 5 negative in the insulating layer 6 is smaller than the saturated state. Then, if the positive value is set to a value smaller than 4, the above-mentioned saturated polarization is obtained in which the interface side with the region 5 is positive in the insulating layer 6, and the above-mentioned first inversion layer is formed in the region 5a. is obtained, and as a result, the current ID is obtained at the above-mentioned value in the saturated state.

Therefore, if a voltage having a value of 4 or more of the above-mentioned voltage V'G, which makes the conductive layer 8 side positive, is applied between the conductive layers 13 and 8 as information of "1" in binary representation, the insulation The polarization in the saturated state in which the interface side with the semiconductor region 5 is positive in the layer 6 is obtained as a binary display that can store information of "1", and from this, the conductive layer 13 and the conductive layer 8 are The above-mentioned value of voltage V'G that makes the side of the insulation layer 8 negative ■ If a voltage having a value of 1 or less is given as information of "O" in binary representation, the side of the interface with the region 5 will be made negative on the insulating layer 6. The polarization in the saturated state can be obtained by storing IOJ information in a binary display.

In addition, in a state in which the information "1" is stored in the binary display described above, a sufficient amount of water is added between the conductive layers 13 and 9 to form the second inversion layer described above in which the conductive layer 9 side is positive. In this case, the above-mentioned first inversion layer in the region 5a becomes
Because of this shape, a conductive state between the semiconductor regions 3 and 4 is obtained, and this can therefore be interpreted as reading out the storage of information of "1".

Furthermore, if the voltage described above is applied between the conductive layers 13 and 9 while the rOJ information is stored in the binary display described above, in this case, the first inversion layer described above is formed in the region 5a. Therefore, a non-conducting state is obtained between the semiconductor regions 3 and 4, and therefore, this can be regarded as reading out the storage of "0" information.

Furthermore, if a voltage smaller than the above-mentioned voltage value is applied between the conductive layers 13 and 9 and is sufficient to prevent the formation of the above-mentioned second inversion layer in the region 5b, the voltage between the semiconductor regions 3 and 4 can be increased. A non-conducting state is obtained, and this therefore results in the above-mentioned 2
This can be a so-called non-access state in which neither "1" in the value display nor rOJ information is read.

The collapse of the memory of "1" and "0" information in the binary display mentioned above is also caused by the above-mentioned voltage V'G between the conductive layers 13 and 8.
Applying a voltage with a value between ■2 and ■3,
Alternatively, the above-mentioned information storage state can be maintained even if no voltage is applied between the conductive layers 13 and 8.

Therefore, in the case of the field effect transistor according to the present invention as described above in FIG. It is something that you have.

For this reason, in the case of the field effect transistor according to the present invention as shown in FIG. Therefore, when constructing such a memory circuit, it is possible to reduce the size of the memory circuit, and to increase the speed of writing and reading information to and from the memory circuit. It has the unique feature that the voltage required for writing or rewriting can be reduced, making it extremely suitable for application to the construction of memory circuits.

Next, a second embodiment of the field effect transistor according to the present invention will be described with reference to FIG. 3. Parts corresponding to those in FIG. In the structure described above in the figure, the region where the insulating layer 12 covers the insulating layer 6 and the conductive layer 8 is omitted, and the conductive layer 8 and the insulating layer disposed on the insulating layer 6 are omitted. FIG. 1 except that instead of the conductive layer 9 disposed on the layer 7, a conductive layer 15 common to the insulating layers 6 and 7 is disposed extending over the insulating layers 6 and 7. It has the same structure as in the case of .

The above is the structure of the second embodiment of the field effect transistor according to the present invention. According to this structure, it has the same structure as the case of FIG. 1 except for the matters mentioned above. Although a detailed explanation will be omitted, similar to the case of FIG. In the value display, “
If information of "1" is given, a state is obtained in which information of "1" can be stored as in the case of FIG.
The above-mentioned value of voltage V'G that makes the side of the conductive layer 15 negative between the two ■ If information of "0" having a value of 1 or less is given, IOJ information can be stored as in the case of FIG. 1. is obtained.

In addition, if the thickness and material of the insulating layer 7 are appropriately selected, the first
Similar to the case in the figure, with the information "1" mentioned above stored, a voltage of a value smaller than the above-mentioned value ■4 is applied between the conductive layers 13 and 15 to make the conductive layer 15 side positive. As a result, an inversion layer similar to the above-mentioned second inversion layer is obtained on the surface side of the region 5b, and a conductive state between the semiconductor regions 3 and 4 is obtained as in the case of FIG. This can be considered as reading out the memory of the information.

Furthermore, if the above-mentioned voltage is applied between the conductive layers 13 and 15 while the above-mentioned "0" information is stored, the above-mentioned inversion layer can be obtained on the surface side of the region 5b. Since the first inversion layer is not formed on the surface side, a non-conducting state is obtained between regions 3 and 4 as in the case of FIG. 1, and the memory of the information "O" is read out. It is possible to do so.

Furthermore, if a voltage that is more negative than the above-mentioned voltage V'G value 2 is applied between the conductive layers 13 and 15, a non-conducting state between regions 3 and 4 is obtained, similar to the case in FIG. This can be a so-called non-access state.

Also, the collapse of the memory of the information of "1" and "0" mentioned above,
As in the case of FIG. 1, the voltage ■ between conductive layers 13 and 15
If a voltage having a value between ``2'' and ``3'' of G is applied, the above-mentioned storage state of the information will be maintained as in the case of FIG.

Therefore, although detailed explanation will be omitted, in the case of the field effect transistor according to the present invention described above in FIG.
It has the same excellent features as the case shown in the figure.

In the above description, it has been stated that the charge accumulating insulating layer 6 includes a ferroelectric material in order to have the above-mentioned charge accumulating property. A mode in which the ferroelectric material is dispersed in a normal insulating material such as silicon oxide, which does not have the property of accumulating electric charges, and a mode in which a ferroelectric material is formed by dispersing the ferroelectric material in a normal insulating material such as silicon oxide, which does not have the property of accumulating electric charges, and It is possible to adopt an embodiment in which a dielectric layer is interposed.

Further, in the above description, only a few examples of the present invention have been shown, and for example, a case has been described in which the charge accumulating insulating layer 6 is formed to include two ferromagnetic tombs. It can also be formed to contain silicon or silicon nitride or aluminum oxide to have accumulation properties.

The "P" and rNJ mentioned above may be read as rNJ and "P", respectively, and various other modifications may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of a field effect transistor according to the present invention, FIG. 2 is a diagram showing the relationship between voltage V'G and current D, and FIG. The figure is a cross-sectional view showing a second embodiment of a field effect transistor according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a main surface, 3, 4, 5, 5a and 5b are semiconductor regions, 6 is a charge storage insulating layer, 7 is a non-charge storage insulating layer, 8, 9, 13, 14 and 15
indicate conductive layers, respectively.

Claims (1)

[Claims] 1. In a semiconductor layer having a first conductivity type, first and second semiconductor regions having a second conductivity type opposite to the first conductivity type are formed from the main surface side of the semiconductor layer. A third semiconductor region formed by the semiconductor layer is formed between them as a channel region and a source region and a drain region, respectively.
A charge storage insulating layer and a non-charge storage insulating layer are juxtaposed on the main surface side of the semiconductor region, and a charge storage insulating layer and a non-charge storage insulating layer are provided with separate or A field effect transistor characterized in that a common conductive layer is arranged as a gate electrode. 2. A field effect transistor according to claim 1, wherein the charge storage insulating layer contains a ferroelectric material. 3. A field effect transistor according to claim 1, wherein the charge storage insulating layer contains silicon, silicon nitride, or aluminum oxide. .