JPS584830B2 - Manufacturing method of junction field effect transistor - Google Patents

Description

Detailed Description of the Invention The present invention provides a field effect transistor having a gallium arsenide aluminum (GaAlAs) heterojunction region on gallium arsenide (GaAs) and using the heterojunction region as a gate electrode region. The present invention relates to a manufacturing method.

2. Description of the Related Art In recent years, as communication frequency bands have become higher, the frequency of each semiconductor element has been actively increased in the semiconductor field.

Among these, junction field effect transistors (hereinafter simply referred to as GaAsFETs) using gallium arsenide crystals are used as elements for high frequency amplification or oscillation.

) is seen as promising. In the high frequency region, especially in the microwave region, the gate length of a GaAsFET is usually extremely short, about 1 μm. Therefore, diffusion-based p-n junction gate GaAsFETs, which involve abnormally fast diffusion in the lateral direction, are generally not used; GaAsFETs using junctions or heterojunctions have been developed.

In addition to shortening the gate length, factors for improving the high frequency performance of FETs include shortening the distance between the gate electrode and the source and drain electrodes to reduce the resistance between the source and drain.

That is, in an FET with a gate length of about 1 μm, the gate-source or drain distance must be 1 μm or less.

However, in the current normal photoetching technology, each distance is 1
The limit is μm.

Therefore, as is well known, GaAs using Schottky junction
In an FET, the distance between each electrode and the length of the gate electrode are each about 1 μm at the shortest using normal photolithography.

In the case of manufacturing a Schottky junction type FET with an even shorter distance between each electrode and gate length, it is necessary to use an extremely high-grade photomask alignment device, which poses a manufacturing problem that makes it unprofitable.

On the other hand, a heterojunction gate FE made of GaAlAs-GaAs can be manufactured by the manufacturing process shown in FIG.
T is intended to solve the above problem.

Now, the manufacturing process of the heterojunction gate FET shown in FIG. 1 will be briefly described below.

First, an n-type GaAs layer 2 and a p-type GaAlAs layer 3 are successively epitaxially grown on a semi-insulating GaAs substrate 1 (FIG. 1A).

A thick metal film 4 is deposited on this epitaxial wafer (FIG. 4b).

Next, a resist film 5 is applied to the gate electrode portion using photolithography, and then the metal film 4 is etched (FIG. C).

Furthermore, using the metal film 4 as a mask, the GaAlAB layer 3 is selectively etched into a so-called undercut shape, and the resist film is removed (d in the same figure).

Finally, when electrode metal for the source and drain is vacuum-deposited over the entire surface, the source 6, gate 7, and drain 8 are formed by a so-called cellular alignment method in which the deposited metal is automatically separated at the eaves-like part of the metal film 4 in the gate area. Ru.

In this way, the above manufacturing process of the heterojunction gate FET is basically a single mask process, and the gate and the distance between the gate, source, and drain electrodes are controlled only by the amount of selective corrosion of the GaAlAs layer 3 (the same Figure d).

Therefore, in order to achieve the gate length of 1 μm and the distance between each electrode of 1 μm or less required for a microwave band FET,
Application of ordinary photolithography technology and a photomask with a gate length of about 2 to 3 μm is sufficient.

Therefore, if a GaAsFET with Peter junction gate structure is
It has great advantages in terms of high performance and industrialization.

The present invention provides a heterojunction gate FET having the above characteristics.
The present invention provides a method for manufacturing a high-performance FET in which the gate length and the distance between the gate electrode and the source and drain electrodes can be controlled in a short and highly accurate manner.

Now, GaAlAs-GaAs hetero edge gate FE
When forming the gate electrode during the manufacturing process of T (Fig. 1 d)
), the GaAlAa layer 3 is corroded into a desired shape using a so-called selective etchant that corrodes only GaAlAs.

For example, hydrochloric acid (HCl) is added to this GaAlAs selective etchant.
When the GaAIAs layer on the (100) plane is corroded using a mixed solution of and phosphoric acid (H3PO4), <011>, <011
It was found that the corrosion rate differs depending on the crystal orientation as shown in Figure 2a.

That is, as can be seen in Figure 2 a, HCl and H3PO
The corrosion rate in the <011> direction due to the mixed solution with No. 4 (volume ratio: 1) is approximately twice the corrosion rate in the <011> direction.

Therefore, GaA7As3 consisting of (100) plane and GaA
Etching the heteroepitaxial crystal with s2 into the heterojunction gate FET using a mask (e.g. metal film 4)
In the process of manufacturing the HC, the direction of the conductive channel is aligned with the <011> direction as shown in FIG.
When the etching mask GaAlAs layer 3 is etched using a mixed etchant of L and H3PO4, the direction of the conductive channel having the same dimensions as above is aligned with the crystal direction other than the <011> axis (for example, the <011> direction). It has been found that a heterojunction gate FET with a shorter gate length than that shown in FIG. 2b can be obtained.

The GaAsFET using the heterojunction of GaAlAs and GaAs as the gate produced as described above has the following effects.

Since a gate length smaller than the mask dimension can be obtained, high frequency performance is improved.

Furthermore, if the gate electrode is corroded so that the gate length direction is aligned with a specific crystal axis direction, the cross section of the gate electrode becomes constant due to the crystal habit.

That is, a constant gate electrode length can be obtained from a gate mask of the same size.

Next, an FET according to an embodiment of the present invention will be described using the manufacturing process diagram of FIG.

First, semi-insulating (100) plane QaAs is used as the substrate 1, and the impurity concentration is 5 x 1016 cm-3 and the thickness is 0.5.
A μm n-type GaAs layer 2 is used, the Ga:Al ratio is 1, the impurity concentration is approximately 1×1018 cm-3, and the thickness is 1 μm.
aAlAs layer 3 was used.

Titanium (Ti) with a thickness of about 1 μm is coated on the metal film 4 of the gate electrode part.
) membrane was used.

A dilute hydrofluoric acid solution was used as the etching solution for titanium, and a solution of HCl and H3PO4 at a mixing ratio of 1 was used as the selective etching solution for the GaAlAs layer 3.

And source, gate, drain electrode metals 6, 7, 8
using an alloy of gold and germanium.

Using each of the above materials, a heterojunction FET was fabricated by aligning the direction of the conductive channel of a striped photomask with a mask gate length of 3 μm and a gate width of 400 μm to the <011> direction of the epitaxial substrate.
A heterojunction gate FET with a gate length of 1 μm and a gate width of about 400 μm was obtained.

The photomask alignment device used in this manufacturing process was a conventional contact exposure type.

The obtained FET showed excellent characteristics for microwave use.

As described above, the heterojunction gate GaAsFE of the present invention
By using the manufacturing method of T, a high performance FET with a short gate length can be obtained even using conventional photolithography and etching techniques due to the crystal habit of the semiconductor material.

[Brief explanation of the drawing]

Figures 1a to 1e show GaAlAs and GaAs used in the present invention.
Heterojunction gate FET using a petrojunction consisting of
This is a manufacturing process diagram. FIG. 2 shows the main part of an embodiment of the present invention, and FIG.
Mixture of HCl and H3P04 at 0°C (volume ratio:
1) is a graph showing the relationship between the amount of corrosion in the <011> and <011> directions in the (100) plane of a thin layer of GaAlAs (Ga:Al ratio=1) and time. Figures 2b and c show the direction of the conductive channel as <01
1> and <011> directions when corroded by the above-mentioned corrosive liquid. 1... Semi-insulating GaAs substrate, 2...
n-type GaAs layer, 3...P-type GaAlAs layer,
4... Metal film, 5... Photoresist film, 6... Source electrode, 7... Gate electrode, 8... Drain electrode.

Claims (1)

[Claims] 1 A step of forming a gallium aluminum arsenide layer on a gallium arsenide crystal having a (100) plane, and using a mixed solution of hydrochloric acid and phosphoric acid, the gallium aluminum arsenide layer is aligned with the <011> crystal axis. forming a heterojunction gate region by selectively etching to leave a striated structure in a direction perpendicular to the direction; and etching a source and a drain on the gallium arsenide crystal across the heterojunction gate region. 1. A method for manufacturing a junction field effect transistor, comprising: providing each electrode region.