JPS5849014B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a method for manufacturing an integrated circuit having different thicknesses of an epitaxially grown layer or a different depth of a buried layer.

Transistors included in conventional semiconductor integrated circuits, for example, are formed in a nearly uniform n-type low impurity density layer on a p-type substrate, which limits the range of characteristics that can be controlled, resulting in higher performance. It was not possible to make it multifunctional.

Therefore, forming a recess in the n-type low impurity density layer,
For example, the depth of the n-type high impurity density buried region has been changed.

However, these methods increase and complicate the number of steps such as photolithography, diffusion, and growth, and are disadvantageous in terms of microfabrication and yield.

FIG. 1 is a partial cross-sectional view of an integrated circuit for explaining an example of a conventional manufacturing method, in which two static induction transistors (SIT) T with different thicknesses of the n-evitaxial growth layer 3 are shown.
1 and T2 are shown.

For example, SITT1 is an inverted type, the source electrode S1 is exposed to the surface through the n+ buried layer 2 and the n+ pull-out region 102, and the SITT2 is the source electrode S2.
The drain electrode D2 is an erect type in which the drain electrode D2 is on the surface side, and the drain electrode D2 is drawn out onto the surface via the n0 buried layer 12, the n0 region formed along the side wall of the recess and the surface.

Further, SITT1 and T2 are separated by a deep P sufficient delamination 101 that almost reaches the P type substrate 1.

In this example, the thickness of the n-region of SITT1 is SITT2
An example is shown in which the gut P regions 4 and 14 are thicker than that of the drain n region 5 and the north n region 15, respectively.
This figure shows an example of a so-called planar type formed on almost the same plane as the .

Furthermore, the isolation of each element is not performed by such a Pn junction, but also by a deep recess that reaches the substrate 1, a thick insulating film, or the like.

FIG. 2 shows a cross-sectional view along the manufacturing process of the conventional integrated circuit shown in FIG.

In FIG. 2a, after forming n+ regions 2 and 12 on a P-type Si substrate by selective diffusion, the entire Si surface is exposed and an n-type growth layer 3 is deposited by epitaxial growth.

Due to the high temperature treatment and redistribution of impurities during the lengthening process, the n0 buried layers 2 and 12 are lifted to the growth layer side.

The surface is oxidized to form the Si02 film 6, and selectively P+ and n+ diffusion layers 101 and 102 are formed, respectively.

Since the formation of these diffusion layers 101 and 102 requires deep heat treatment at high temperatures for a long time, re-diffusion of the buried layers 2 and 12 is significant, resulting in a gentle impurity density distribution on the growth layer 3 side. This results in poor breakdown voltage, increased capacitance, and deterioration of frequency characteristics.

In order to carry out deeper diffusion, the lateral spread increases to approximately twice the thickness of the grown layer, and the occupied widths of the P-sufficiently separated region 101 and the drawn-out n-sufficient region 102 cannot be ignored, making it difficult to improve the integration density. was giving.

FIG. 2b shows a cross-sectional view after selectively etching the n-type growth layer 3 for SITT 2 to make it thinner and partially selectively etching it to form the drain extraction region 112 and oxidizing it.

During selective etching, the etched area also expands in the lateral direction, so this process also reduces the integration density.

Next, FIG. 2C is a cross-sectional view after the gate P regions 4 and 14 of SITT1 and T2 are formed by selective diffusion.

In FIG. 2d, the drain n is again selectively etched.
After further increasing the depth of the recess so as to almost reach the tenth region 12, oxidation is performed again to open Si02 holes and perform selective diffusion.
This is a cross-sectional view after forming the drain n+ region 5 of SITT, the source n+ region 15 of SITT2, and the drain n+ region 112 of SITT2.

Chemical hot etching (HF) is used for selective etching of semiconductors.
-HNO3-based, KOH, etc.), plasma.
Sex and spat. Conventional methods such as dry etching such as etching or gas etching such as HCt can be used.

After the above steps, contact holes are made and metal vapor deposition is performed.
This will be completed by selective etching for wiring.

As described above, simply manufacturing SITs with different thicknesses of the n-type growth layer 3 causes problems such as an increase in heat treatment time, a resulting decrease in integration density, an increase in the number of times of Si etching, and an increase in the number of steps involved. It had become.

Similar examples include n-channel SIT and n-channel SIT.
pn bipolar. It exists in all integrated circuits in which different growth layer thicknesses are desired, such as integrated circuits in which transistors (BJTs) are mixed, BJT integrated circuits, and FET integrated circuits, and the same applies to those in which each conductivity type is reversed.

The present invention provides a manufacturing method that improves the above-mentioned problems, and the surface is almost flat, separation and buried layer extraction can be easily performed, and therefore it is possible to increase the integration density.

The manufacturing method of the present invention is characterized by layered growth (La
It is necessary to appropriately select the crystal orientation of the substrate and the epitaxial growth conditions (raw material temperature, material supply amount, flow rate, etc. are the main factors in the CVD method).

First, the layered growth utilized in the present invention will be briefly described using FIG.

The epitaxial growth of semiconductor crystals such as Si and GOAS is due to the layered growth mechanism, as reported in Semiconductor Research Vol. 7, 131.
Tribute to 165 Tribute (1971), Volume 11, 55 Tribute to 8
This is described in 6 Mitsugu (1975).

In this growth mechanism, (111), (113), (1
10), (112), and (100), the lateral growth rate is extremely fast, reaching approximately 100 to 1000 times as much as the growth rate in the vertical direction on specific low-index crystal planes.

Therefore, these crystal planes have a difference of about 0.0 mm from a perfect crystal plane.
A flat growth surface on an atomic scale with a deviation of less than 2, so-called facets, is formed.

If an uneven surface is provided on such a facet, for example as shown in FIG. 3A, and growth is performed for a short period of time, the depression will be immediately filled.

Since the lateral growth rate reaches several 100 μMH, the width is 100 μMH.
A dent of less than μm will be filled within 1 minute.
Not even 1 μm is deposited in the vertical direction.

When a board like the one shown in Figure 3a is used, at the beginning, the third
As shown in FIG. b, the recess is filled from the bottom, and at the same time, a mound-shaped growth nucleus P is generated on the surface a certain distance from the side surface of the recess.

This is because atoms adsorbed on the surface migrate and move to a stable step, but if there are no steps nearby, some atoms gather together to form a growth nucleus.

Half of the average distance between growing nuclei 2L1 (-πL2, N: density of growing nuclei), that is, N L, is approximately equal to the migration distance of atoms, so it is difficult for growing nuclei to occur within L from the step, and most The atoms will contribute to lateral growth (layered growth).

In other ranges, Kaicho nuclei are generated and have a vertical growth component.

Therefore, when the width of the bottom surface is smaller than 2L, it grows flat until there is no difference in level, and similarly, when the width b of the top surface is smaller than 2L, there is almost no growth on the top surface.

On the other hand, when the widths a and b are each larger than 2L, the growth occurs in the vertical direction, albeit slowly, due to the generation of growth nuclei. An example of the schematic diagram is shown in FIG. 3C.

The distance 2L between growth nuclei changes depending on the growth conditions, and the higher the growth rate, the thicker it becomes, and the larger the amount of raw material supplied, the smaller it becomes.
Journal of Crystal Growth
alOf・Crystal・Growth) Volume 31 2
An example of this is described in 90th Edition Fig. 7 (1975).

In the hydrogen reduction method of SiCl4, 2L is (111) at 1200°C, and the Si
The same is true for H4, for example, (100) is a journal
Journal of Crystal Growth
・Crystal-Growth) Volumes 3 and 4 4
3, 3 (1968) and Semiconductor Research Vol. 11, 69, Figure 3, 3
1 and Figure 3. 32 (1975).

The present invention actively utilizes the above-mentioned phenomenon, and as a result, an example of an integrated circuit structure as shown in FIG. 4 is realized corresponding to that in FIG. 1.

In FIG. 4, as in FIG. 1, the thickness of the n region is different.
There are ITT1 and T2, which are separated by a P-type substrate 1.

Further, an example is shown in which the lead-outs of the buried n-regions 2 and 12 are formed by n+ regions 102 and 112 on the front surface.

FIG. 5 specifically explains the manufacturing method according to the present invention with respect to the structure shown in FIG. 4.

FIG. 5a shows a cross section of a P-type substrate 1 by selective Si etching to form recesses where SITTs 1 and T2 are to be formed, and then to form diffusion layers 2 and 12, which will become buried layers.

In FIG. 5b, a portion of the Si02 film (or insulating film such as Si3N film) 6 on the side wall of the concave portion is left on the side near the top surface of the convex portion by photolithography after oxidation again.

In this case, it is desirable that the side walls of the recess are not perpendicular to the surface, and the recess should be etched using wet or dry isotropic etching or (100) etching.
It can be formed by anisotropic etching using an alkaline aqueous solution with the (111) plane as the main surface and the (111) plane as the side wall.

Further, the end portion of the opening of the insulating film 6 left on the side wall of the recess is made to approximately match the height of the surface of the growth layer.

A cross-sectional view of the grown substrate 1 is shown in FIG. 5C.
The concave portion is filled by rapid lateral growth, and since there is no exposed Si and no steps above the opening end of the insulating film 60, there is almost no growth, so that growth virtually stops.

Therefore, vertical growth is more effectively stopped when the width of the recess is narrower than the average growth nucleation interval 2L.

Depending on the height of the insulating film 6 left on the side wall of the recess, growth layers 3 and 13 with different thicknesses can be obtained in one growth.

In FIG. 5C, the upper surface of the convex portion is covered with an insulating film 6, but this is not necessarily necessary since growth in the vertical direction is slow.

Although a polycrystalline layer may be deposited on the insulating film 6, it is easy to remove because the etching rate is fast, and HCt,
By mixing HBr or the like, it is possible to prevent the deposition.

After the growth, as shown in FIG.
At the same time as forming the source n region 15, the buried drawer n
10 regions 102 and 112 can be formed, and deep n0 diffusion is not required.

Since each element is isolated by the P-type substrate 1, there is also the advantage that deep P-diffusion is not necessary.

As described above, according to the manufacturing method of the present invention, even if there are different regions of the epitaxial growth layer in the same chip, separation and extraction of the buried layer can be easily performed by shallow diffusion or etching (in extreme cases, In addition, the present invention can be carried out as long as there is a side wall of the recess, and since a part of the recess can be used as it is as a separation layer or an arch, the distance between each element can be shortened, and the integration density can be extremely improved.

In the integrated circuit structure example shown in FIG. 4 to which the present invention is applied,
An inverted type SITT1 was formed on the thicker side of the n-region, but the S
As for the characteristics of IT, it is desirable that the series resistance rs between the source electrode and the channel be small, so it is often desirable to form an inverted shape in the thinner n-region.

Furthermore, in the same figure, when drawing out the n+ embedded area, P
Although n0 regions are formed continuously from the bottom surface on the side surface of the recessed portion of the mold substrate 1, this is not necessarily necessary.

In addition, in the present invention, since a part of the P-type substrate 1 is used as an isolation region, the narrower the width of the isolation region and the lower the impurity density, the more likely punch-through will occur, or the parasitic transistor effect will become larger. In order to eliminate this problem, it is also effective to form a P-type diffusion or ion implantation layer on the substrate in advance for higher integration.

As a concrete explanation of the present invention, an example of two vertical SITs with different thicknesses in the n region has been described, but the same applies to three or more types of thickness. Since the growth can be performed in the same way, the present invention can be easily applied to integrated circuits in which n-channel and p-channel coexist with various high-resistance layer thicknesses.

For this reason, the present invention is applicable to devices that include a mixture of SIT, BJT, and FET, devices that consist only of each transistor, devices that are horizontal rather than vertical transistors, and devices that include n-channel, P-channel, pnp, npn transistors, and passive elements. It can be applied to all integrated circuits.

Further, although an example in which each recess has one transistor has been described, the present invention is not limited to this, and it is also possible to include a plurality of transistors or elements in one recess, depending on the separation and extraction electrodes.

The phenomenon used in the present invention is not limited to Si, but also Ge, GaAs,
It is also found in 1-1 composite compounds such as GaP and their mixed crystals, and the growth method is limited to vapor phase growth, liquid phase growth, MBE method, etc. can be used.

The scope of application of the present invention is extremely wide, and along with the above-mentioned advantages, the industrial value is extremely high.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional structure of an integrated circuit including an SIT having n regions with different thicknesses, and FIGS. Cross-sectional view. Figures 3a-c are schematic cross-sectional views for explaining the growth phenomenon used in the present invention, Figure 4 is a cross-sectional view of an integrated circuit structure realized by the present invention, and Figures 5a-d are schematic cross-sectional views for explaining the growth phenomenon used in the present invention, respectively. FIG. 3 is a cross-sectional view for explaining the manufacturing method according to the invention. DESCRIPTION OF SYMBOLS 1... P type Si substrate, 2, 12... n10 buried region, 3, 13... n1 growth layer, 4, 14... gate P10 region, 5, 15... drain or Source n+ region, 6, 16...insulating film, 102, 112...n+
Embedded extraction area, 101...separation area, S1,
S2... source electrode, G1, G2... gate electrode,
D1, D2...Drain electrodes.

Claims (1)

[Scope of Claims] 1. A step of forming a plurality of recesses on the main surface of a semiconductor substrate having a low-index crystal plane with a higher epitaxial growth rate in the lateral direction than in the vertical direction, and forming a plurality of recesses on the main surface of the substrate and the bottom and side surfaces of the recesses. covering with an insulating film, and removing the insulating film from the bottom surface to a predetermined height from the bottom surface of the insulating film on the bottom surface of the recessed portion and the insulating film on the side surface of the recessed portion to cover the predetermined height of at least one recessed portion and the insulating film on the side surface of the recessed portion. A semiconductor integrated circuit device comprising the steps of: making the predetermined heights different; and forming a growth layer having a different thickness depending on the predetermined height by subjecting the recess to epitaxial growth exhibiting layered growth. manufacturing method. 2. The semiconductor integrated device according to claim 1, wherein the width of the narrowest bottom surface of each of the plurality of recesses is selected to be equal to or less than the growth nucleation interval determined by the eviquitaxial growth conditions. Manufacturing method for manufacturing circuits.