JPS5849018B2 - Method of forming electrode pattern - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming an electrode pattern, and provides a method of forming an electrode pattern of a semiconductor device by a so-called lift-off method.

Methods for forming an Au electrode on the surface of a semiconductor device, such as a double-diffused planar transistor for high frequency use, include etching or lift-off. However, the former method is not preferred because it is difficult to microfabricate the electrode and also requires plating, while the latter method has the drawback that stable microfabrication of the electrode is not possible.

This lift-off method will be explained with reference to FIGS. 1 and 2.

In FIG. 1, comb-shaped electrode patterns 2 and 3 are placed on a Si02 layer 1 existing on the surface of a semiconductor substrate (not shown) that has been subjected to a diffusion process, in contact with a diffusion region.
However, these electrode patterns have comb teeth portions 2a facing each other with an extremely narrow gap 4 of about 2μ.
, 3a, and bonding pad portions 2b, 3b.

To form such electrode patterns 2 and 3,
First, a photoresist layer 5 with a pattern opposite to that of the electrode patterns 2 and 3 is coated on the SiO layer 1, and in this state, as shown in FIG.
Vapor-deposited metal layers 7, 8 are applied to the surface of the semiconductor substrate under the opening (not shown) in layer 2 1 and this Si02 layer, and to the surface of the photoresist layer 5.

Thereafter, only the vapor-deposited metal layer 8 on the top surface can be selectively peeled off along with the photoresist layer 5 by using adhesive tape or by applying ultrasonic waves in a solvent. As a result, an ultrafine structure as shown in FIG. 1 is formed. The electrode patterns 2 and 3 can remain.

In this case, the SiO layer 1 and the vapor-deposited metal layer 7 directly deposited on the semiconductor substrate, that is, the electrode patterns 2 and 3, are firmly adhered to each other, and therefore remain as they are without peeling off.

Such a lift-off method is particularly difficult when forming an electrode with an ultra-fine structure such as in a high-frequency transistor or an electrode with a three-layer structure of TiPt-Au such as an Au electrode.

In order to lower the current density and improve reliability, the electrode needs to have a certain thickness, and in the case of an Au electrode, Ti and Pt (or Mo
s W ) between them, which also increases the thickness of the electrode.

In the case of this three-layer structure, due to the difference in coefficient of thermal expansion between the three types of metals, when exposed to heat, it acts like a bimetal, and stress is generated in the metal layers.

Considering these points, the performance required for the material of the photoresist layer 5 is as follows: (1) It should have sufficient resolution even if the film thickness after coating is increased.

(The edges should be sharp and the sides should be straight after application.)

(3) It has an appropriate adhesive strength, never peels off until the electrode metal is deposited, and then peels off easily.

However, there is a problem particularly with respect to the third adhesive strength, and if a photoresist with weak adhesive strength is used, the resist will peel off during vapor deposition, making it impossible to form a predetermined pattern.

To explain this phenomenon in detail with reference to FIG. 2, stress generated in the metal during vapor deposition of the electrode metal causes the photoresist layer to
A twitching phenomenon occurs, and as a result, the ends of the photoresist layer 5 curl up and become deformed.

This is likely to occur if the photoresist layer 5 side has a large area, and does not occur at all in the gap 4 (see FIG. 1) because the electrode metal is in close contact with the underlying substrate in the immediate vicinity, but especially in the area 9. In the butt portions 2b and 3b, the vapor-deposited metal layer curls up and shrinks as shown by the arrow.

In this way, the photoresist layer 5 is deformed and floated due to the stress of the vapor-deposited metal layer 8, so that the gap 10
The vapor-deposited electrode metal 6 gradually enters into the desired electrode width W.
spreads to both sides, making the electrode pattern blurry.

As a result, considerable deformation was observed in the electrode pattern shown in FIG.
It was observed that pad portion 2b and pad portion 3a were short-circuited, and pad portion 2b
It was also found that the outline of the periphery of , 3b became faint and was considerably deformed.

The present invention was invented to correct the above-mentioned defects, and includes a step of providing an insulating layer (e.g., SiO&) on a semiconductor layer, and a step of providing a mask material layer (e.g., a photoresist layer) on this insulating layer. a step of removing a portion of this mask material layer where an electrode is to be formed to provide a first cutout (i.e. an opening for electrode material deposition); a step of partially removing the mask material layer to provide a second cutout, a step of vapor depositing an electrode material layer over the entire surface including the insulating layer and the mask material layer, and the mask material layer. and a step of selectively removing the electrode material layer thereon.

By this method, deformation of the electrode pattern due to the shrinkage phenomenon of the vapor-deposited electrode material can be prevented, and fine processing of the electrode can be stably performed.

Next, an example in which the present invention is applied to an electrode pattern of a high frequency transistor will be described with reference to FIGS. 3 and 4.

In this embodiment, parts common to those shown in FIG. 1 are given common reference numerals, and explanations thereof will be omitted.

According to this embodiment, as shown in FIG.
, 3, an auxiliary pattern 11 for preventing deformation of the electrode is provided near a portion 9 where deformation is particularly likely to occur.

This auxiliary pattern does not affect the electrical performance of the semiconductor element at all (that is, it does not have a negative effect), and after the photoresist layer is peeled off after the electrode metal is deposited (described later), the Si02
This is an island-shaped metal layer left on top of the layer.

In addition, a metal layer 12 made of electrode metal and completely electrically floating is formed on Si so as to surround the periphery of the semiconductor element.
Formed on layer 02.

Next, the state of the auxiliary pattern 11 at the time when the electrode patterns 2 and 3 are formed by vapor deposition will be explained with reference to FIG.

At this point, the N-type silicon semiconductor substrate 13 has already been exposed to P.
For example, the base region 14 of the mold is diffused, and the Si02 layer 1 having a diffusion opening 15 is formed on the surface of the substrate 130.

A photoresist layer 5 is then formed in a predetermined pattern on the surface of this Si02 layer by a conventionally known method.

At this time, of the photoresist layer 5 existing at the position corresponding to the above-mentioned portion 9, a portion close to the electrode patterns 2 and 3 is selectively removed, and an opening 15 is formed by photoetching.

In this state, electrode metal 6 is deposited to form a deposited metal layer 7 over the entire surface.

This metal layer is deposited over the entire surface including the electrode pattern openings 16 and 15 formed in the photoresist layer 5.

However, even if the photoresist layer 5 tries to peel up due to the stress of the metal layer 7 as shown in FIG. Therefore, this deformation at the right end portion 5a of the photoresist layer 5 is prevented.

As a result, the right end portion 5a of the photoresist layer 5 is in close contact with the Si02 layer 1, and the effect of the strain caused by the metal layer 7 is directed in the direction of the arrow 170,000 in FIG. 3, and the effect substantially appears on the right end portion 5a. There isn't.

Therefore, the portion of the metal layer 7 deposited within the opening 15 of the photoresist layer 5, ie the metal layer 11, is removed from the photoresist layer 5.
This will serve as a kind of cushion to prevent deformation.

In this way, since deformation of the photoresist layer 5 is prevented in the portion 9, the masking effect on the vapor-deposited metal is improved, and it is possible to prevent both electrode patterns 2 and 3 from short-circuiting. It is possible to form fine electrode patterns 2 and 3 with high precision.

Further, the metal layer 12 is formed by forming an opening (not shown) similar to the opening 15 in the photoresist layer 5 around the opening and depositing the electrode metal 6 (see FIG. 4) in the opening. It is formed by

It is desirable that this metal layer 12 be formed as close to the semiconductor element as possible.

That is, the area of the pad portions 2b, 3b of the electrode patterns 2, 3 can be regulated by the metal layer 12 to be accurate and small.

As a result, the element according to this embodiment can be housed in the metal layer 12 separately from other adjacent elements, and the metal layer 12 can also eliminate the influence of the shrinkage phenomenon of the vapor-deposited metal in the parts of other elements.

Regarding the outside of the metal layer 12, the influence of the evaporated metal constriction appears in the direction of the arrow 18;
3 has no effect on all.

Incidentally, the vapor deposited metal layer 7 is actually made of Ti of 1500 to 200 oi, PT of 2000 to 3000X, and 7oooi to 1μ.
It has a three-layer structure formed by successive vapor deposition of Au and Au.

To form the electrode patterns 2 and 3 from the state shown in FIG. 4, adhesive tape is pasted on the surface and then peeled off. This allows the vapor-deposited metal on the top surface to be peeled off at the same time as the photoresist layer 5. In this way, only the electrode patterns 2 and 3 and the metal layers 11 and 12 can remain.

In addition, in order to eliminate the effects of twitching of the deposited metal,
The position of the metal layer 11 is preferably as close as possible to the electrode patterns 2 and 3, and for example, it is desirable that the distance therebetween is 2 to 4 μ.

Although the present invention has been described above based on one embodiment, it will be understood that the present invention is not limited to this embodiment and can be further modified based on the technical idea thereof.

For example, the number, location and shape of the openings 15 in the photoresist layer may be changed, and the openings 15 may penetrate through the Si02 layer 1 to reach the substrate 13.

As described above, in the present invention, the second cutout is provided in the vicinity of the first cutout in the mask material layer for forming an electrode pattern, and the vapor deposition is performed in this state. The removed portion effectively prevents the straining phenomenon of the mask material layer due to stress generated in the vapor deposition material, so that the electrode pattern becomes a desired pattern without being deformed, and in particular, fine processing of the electrode can be carried out stably.

[Brief explanation of the drawing]

FIGS. 1 and 2 show a conventional example, in which FIG. 1 is a plan view of an electrode pattern, and FIG. 2 is a sectional view of a main part for explaining the twitching phenomenon that occurs during vapor deposition. 3 and 4 show an example in which the present invention is applied to a high frequency transistor, in which FIG. 3 is a plan view of an electrode pattern, and FIG. It is a sectional view taken along the line IV-IV. In addition, in the symbols used in the drawings, 1 represents Si02
layers, 2 and 3 are electrode patterns, 5 is a photoresist layer,
7 is a vapor deposited metal layer, and 11 is an auxiliary pattern.

Claims (1)

[Claims] 1. A step of providing an insulating layer on a semiconductor layer, a step of providing a mask material layer on this insulating layer, and a step of removing a portion of this mask material layer where an electrode is to be formed to provide a first cutout portion. and a step of partially removing the mask material layer in the vicinity of the first cutout to provide a second cutout, and forming an electrode over the entire surface including the insulating layer and the mask material layer. A method for forming an electrode pattern, comprising the steps of forming a material layer by vapor deposition, and selectively removing the mask material layer and the electrode material layer thereon.