JPS5850020B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5850020B2 JPS5850020B2 JP54056942A JP5694279A JPS5850020B2 JP S5850020 B2 JPS5850020 B2 JP S5850020B2 JP 54056942 A JP54056942 A JP 54056942A JP 5694279 A JP5694279 A JP 5694279A JP S5850020 B2 JPS5850020 B2 JP S5850020B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- electrode
- protruding electrode
- protective film
- fluororesin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
半導体素子と電気的につながる外部リード線の接続方法
において、半導体素子上の電極端子に高さが10〜20
μの金の突起状の電極を設け、これに外部リードとなる
金属箔からなるステムを熱圧着する方法が用いられる。In a method for connecting an external lead wire that is electrically connected to a semiconductor element, the electrode terminal on the semiconductor element has a height of 10 to 20 mm.
A method is used in which a protruding gold electrode of μ is provided and a stem made of metal foil, which serves as an external lead, is thermocompression bonded to the protruding electrode.
この接続方法において、半導体素子上に突起状の電極を
形成するにあたり素子の内部配線を保護する必要から電
極端子を除(半導体表面の全面に保護膜を設ける。In this connection method, when forming protruding electrodes on a semiconductor element, the electrode terminals are removed because it is necessary to protect the internal wiring of the element (a protective film is provided over the entire surface of the semiconductor).
従来この保護膜には、ガラスが用いられ、電極を形成す
る際に使用する各種の化学薬品によって素子の内部が侵
かされることを防ぐと同時に、半導体素子の特性を永続
的に安定動作させる為の保護の役目も果している。Conventionally, this protective film is made of glass, which prevents the inside of the device from being attacked by the various chemicals used to form the electrodes, and at the same time maintains the properties of the semiconductor device in a permanently stable manner. It also plays a protective role.
このような役目をもつガラス保護膜は、加工性に優ぐれ
ている、電気的に絶縁性が高い、耐薬品性がある等の利
点をもつ。A glass protective film having such a role has advantages such as excellent workability, high electrical insulation, and chemical resistance.
一方で無相張係数の異なる半導体、金属などの上に形成
されるのでガラス特有の割れ易い性質が決定的な欠点と
なる。On the other hand, since it is formed on semiconductors, metals, etc. that have different incompatibility coefficients, the breakable property peculiar to glass becomes a decisive drawback.
半導体素子の実装工程における加熱処理あるいは、使用
環境の変化などによる熱衝撃によってひび割れを生じ、
この為素子特性の劣化を招き信頼性を低下させる原因と
なっている。Cracks may occur due to heat treatment during the semiconductor element mounting process or thermal shock due to changes in the usage environment.
This causes deterioration of device characteristics and decreases reliability.
本発明は、半導体素子表面の保護膜に関するもので、ガ
ラス保護膜のもつ欠点を補ないリード接続の加工工程で
の歩留りを向上すると共に、素子特性の永続的安定動作
を実現可能な半導体装置の製造方法を提供するものであ
る。The present invention relates to a protective film on the surface of a semiconductor element, which improves the yield in the lead connection processing process by compensating for the drawbacks of a glass protective film, and is capable of producing a semiconductor device that can permanently maintain stable operation of the element characteristics. A manufacturing method is provided.
以下に、本発明の詳細を図面により説明する。The details of the present invention will be explained below with reference to the drawings.
第1図は、従来のガラス保護膜をもつ半導体素子のリー
ド接続の断面図である。FIG. 1 is a sectional view of a lead connection of a semiconductor device having a conventional glass protective film.
即ち、半導体素子10表面には、内部配線としての金属
膜電極2が設げられている。That is, a metal film electrode 2 as an internal wiring is provided on the surface of the semiconductor element 10.
この金属電極上には外部接続電極3を除く全面にガラス
保護膜4を例えば化学蒸着方法で1〜2μの厚さに形成
する。A glass protective film 4 with a thickness of 1 to 2 μm is formed on the entire surface of the metal electrode except for the external connection electrode 3 by, for example, a chemical vapor deposition method.
又、外部接続電極3については、ガラス保護膜4を形成
した後に金を選択的に10〜20μの厚さに電気メッキ
などを用いて突起電極5を形成する。Regarding the external connection electrode 3, after forming the glass protective film 4, a protruding electrode 5 is formed by selectively applying gold to a thickness of 10 to 20 microns using electroplating or the like.
一方あらかじめ外部リード線としては、ステムの形状に
作られた銅箔6上に錫7又はAuをメッキしておき、こ
のリード6と突起電極5とを熱圧着してリードの接続を
行なう。On the other hand, as an external lead wire, tin 7 or Au is plated on a copper foil 6 formed in the shape of a stem in advance, and the lead 6 and the protruding electrode 5 are bonded by thermocompression to connect the leads.
外部リードの熱圧着工程に関して例えば、銅6上に錫7
メツキしたリード線においては、Au−8n の共晶温
度(280℃)以上に加熱することによって接合部に共
晶半田を生成しリード接続をする。Regarding the thermocompression bonding process of external leads, for example, tin 7 on copper 6
The plated lead wires are heated to a temperature higher than the eutectic temperature of Au-8n (280 DEG C.) to form eutectic solder at the joint and connect the leads.
又、Au 7メツキのCu81J−ドを用いる場合には
、300℃以上の加熱抑圧によって、Au−Au のリ
ードが接続される。Further, when using a Cu81J-board plated with Au7, the Au-Au leads are connected by suppressing heating to 300°C or higher.
いづれの場合においても半導体素子には加熱抑圧による
衝撃が加わり、電極周辺において、ガラス保護膜にひび
割れが生じ易い。In either case, a shock due to heat suppression is applied to the semiconductor element, and cracks are likely to occur in the glass protective film around the electrodes.
このひび割れは、それ自体、電気特性に影響を及ぼすも
のでないが、永続的に安定動体を維持する為の半導体素
子の汚染に対する保護効果はなくなり、信頼性は著しる
しく低下する。Although this crack itself does not affect the electrical characteristics, the effect of protecting the semiconductor element from contamination to permanently maintain a stable moving body is lost, and the reliability is significantly reduced.
一方第2−2図は、本発明による保護膜を具備した半導
体素子とこれに外部リードを接続したものの断面図であ
る。On the other hand, FIG. 2-2 is a sectional view of a semiconductor element provided with a protective film according to the present invention and an external lead connected thereto.
突起電極5を形成するまでは全〈従来の方法と変らない
3即ち、半導体素子の外部接続素子3上には厚さ10〜
20μのAuの突起電極5が形成されていて、他の表面
は、1〜2μのガラス保護膜で被覆されている。Until the protruding electrodes 5 are formed, all steps are the same as in the conventional method.
A protruding electrode 5 of 20 μm of Au is formed, and the other surfaces are covered with a glass protective film of 1 to 2 μm.
本発明においては、第2−1図に示すようにAuの突起
電極5を形成した後に、ガラス保護膜上にさらに保護膜
4を設ける。In the present invention, after forming the Au protruding electrodes 5 as shown in FIG. 2-1, a protective film 4 is further provided on the glass protective film.
この保護膜のフッ素樹脂例えばテフロン樹脂(商品名以
下この商品名を使用する)で形成される。This protective film is made of a fluororesin such as Teflon resin (this product name will be used hereinafter).
即ち、半導体素子表面の全面にわたり、熱可塑性のテフ
ロン樹脂シートをはりつげる。That is, a thermoplastic Teflon resin sheet is pasted over the entire surface of the semiconductor element.
この場合、半導体素子表面は、突起電極、配線などの為
に凹凸の状態にある。In this case, the surface of the semiconductor element is uneven due to protruding electrodes, wiring, and the like.
従って、テフロン樹脂シートのはりつげ工程において、
内部に気泡を内蔵し均一な保護膜の形成が困難と考えら
れがちであるが、次のような方法によって、ガラス保護
膜上に均一な厚さでかつ内部に気泡を内蔵することなく
接着することが容易にできる。Therefore, in the process of gluing Teflon resin sheets,
It is often thought that it is difficult to form a uniform protective film due to the presence of air bubbles inside, but the following method can be used to adhere to the glass protective film with a uniform thickness and without any air bubbles inside. can be done easily.
先ず、100℃〜150℃(テフロン樹脂シートが溶融
しない温度)の熱板上で例えば厚さが10μのテフロン
樹脂シートを突起電極をもつ半導体素子表面に敷き、弾
力性のある材料例えばシリコンゴム板などを用いて抑圧
する。First, a Teflon resin sheet with a thickness of, for example, 10 μm is placed on the surface of a semiconductor element having protruding electrodes on a hot plate at 100°C to 150°C (a temperature at which the Teflon resin sheet does not melt), and an elastic material such as a silicone rubber plate is placed on the surface of the semiconductor element having protruding electrodes. etc. to suppress it.
この工程でテフロン樹脂シートは、半導体素子表面の凹
凸に合うように成形される。In this step, the Teflon resin sheet is shaped to match the irregularities on the surface of the semiconductor element.
次に、この成形した状態で260 ’C〜3oo℃の熱
板上でテフロン樹脂シートを溶融する。Next, in this molded state, the Teflon resin sheet is melted on a hot plate at 260'C to 300C.
半導体素子表面にはあらかじめ表面活性化処理をほどこ
すことによって、溶融軟化したテフロン樹脂は、より強
固に半導体表面の凹凸にそってなじみ一様な厚さでかつ
、気泡を内蔵することなく融着する。By applying a surface activation treatment to the semiconductor element surface in advance, the melted and softened Teflon resin more firmly conforms to the unevenness of the semiconductor surface and fuses to a uniform thickness without incorporating air bubbles. do.
半導体素子表面全面にわたって接着したテフロン樹脂層
について、第2−2図に示すように外部端子電極5に相
当する位置に外部リード接続の為のテフロン樹脂層に穴
を開ける。With respect to the Teflon resin layer adhered over the entire surface of the semiconductor element, a hole is made in the Teflon resin layer for external lead connection at a position corresponding to the external terminal electrode 5, as shown in FIG. 2-2.
テフロン樹脂の加工に関しては、フォトレジスト方法を
用いる。A photoresist method is used for processing the Teflon resin.
テフロン樹脂の蝕刻方法は、例えば酸素気体放電中での
プラズマエツチング方法などを用いる。As a method of etching the Teflon resin, for example, a plasma etching method in oxygen gas discharge is used.
このようにして形成した半導体素子の表面は第2−2図
の如く、外部電極端子を除く全面が、ガラスと70μの
テフロン樹脂層で被覆されることになる。As shown in FIG. 2-2, the entire surface of the semiconductor element thus formed, except for the external electrode terminals, is covered with glass and a 70 μm Teflon resin layer.
本発明による方法で保護された半導体素子に対して外部
リード線を第2−3図のように接続した場合の効果は次
のようになる。The effects when external lead wires are connected as shown in FIGS. 2-3 to the semiconductor element protected by the method according to the present invention are as follows.
(1)テフロン樹脂は化学的に安定であるばかりでなく
、非吸湿性であり、水蒸気の透過率は10μ厚さのフィ
ルムで0.01%以下と極めて小さい。(1) Teflon resin is not only chemically stable but also non-hygroscopic, and its water vapor permeability is extremely low at 0.01% or less for a 10μ thick film.
従って、半導体素子の汚染を永続的に防ぐことができる
。Therefore, contamination of semiconductor elements can be permanently prevented.
又、−250°C〜+200℃の温度範囲で連続的に使
用可能であり、機械的性質としては、強靭で柔軟性があ
り、熱衝撃によるひび割れを発生しない。Further, it can be used continuously in a temperature range of -250°C to +200°C, has strong and flexible mechanical properties, and does not crack due to thermal shock.
(2)半導体素子表面上が厚さ10μのテフロン樹脂で
保護されていることは、半導体素子上の外部接続端子に
接続したリードが、半導体素子の周辺部で接触し電気的
に短絡することを防ぐ効果をもつ。(2) The surface of the semiconductor element is protected by Teflon resin with a thickness of 10 μm, which prevents the leads connected to the external connection terminals on the semiconductor element from coming into contact with the periphery of the semiconductor element and causing an electrical short circuit. It has a preventive effect.
因みは従来、ガラス保護膜を使用した場合ではガラス保
護膜は1〜2μと薄い層にしか形成可能でなく、外部電
極リードが半導体素子と接触し電気的に短絡することに
よる不良が多く発生していた。By the way, in the past, when a glass protective film was used, the glass protective film could only be formed as a thin layer of 1 to 2 μm, and many defects occurred due to the external electrode lead coming into contact with the semiconductor element and causing electrical short circuits. Was.
【図面の簡単な説明】
第1図は従来例を説明するための装置断面図、第2−1
図〜第2−3図は、本発明の一実施例を説明するための
工程図である。
図において、4・・・・・・ガラス被膜、4′・・・・
・・フッ素樹脂層、6・・・・・・リード線。[Brief explanation of the drawings] Fig. 1 is a sectional view of the device for explaining a conventional example, Fig. 2-1
Figures 2-3 are process diagrams for explaining one embodiment of the present invention. In the figure, 4...Glass coating, 4'...
...Fluororesin layer, 6...Lead wire.
Claims (1)
を複数形成する工程と、該複数の金属電極及び露出して
いる半導体素子表面に表面保護膜となるガラス被膜を形
成する工程と、前記複数の金属電極のうち外部接続する
電極上のガラス被膜を除去し、その除去した部分に突出
電極を形成する工程と、該突出電極及び前記ガラス被膜
上にフッ素樹脂を形成し、そのフッ素樹脂を溶融しない
温度で抑圧する工程と、該工程後に加熱し、前記フッ素
樹脂を溶融して前記突出電極及び前記ガラス被膜上に融
着形成する工程と、前記突出電極上のフッ素樹脂を除去
して突出電極を露出せしめ、その露出した突出電極に外
部リード線を接続する工程とを具備してなることを特徴
とする半導体装置の製造方法。1. A step of selectively forming a plurality of metal electrodes as wiring on the surface of a semiconductor element, a step of forming a glass film serving as a surface protection film on the plurality of metal electrodes and the exposed surface of the semiconductor element, and A step of removing the glass coating on the externally connected metal electrode and forming a protruding electrode on the removed portion, forming a fluororesin on the protrusion electrode and the glass coating, and melting the fluororesin. a step of heating after the step to melt the fluororesin and fusion-bond it on the protruding electrode and the glass coating; and a step of removing the fluororesin on the protruding electrode to form the protruding electrode. 1. A method for manufacturing a semiconductor device, comprising the steps of: exposing a protruding electrode; and connecting an external lead wire to the exposed protruding electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54056942A JPS5850020B2 (en) | 1979-05-11 | 1979-05-11 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54056942A JPS5850020B2 (en) | 1979-05-11 | 1979-05-11 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS551190A JPS551190A (en) | 1980-01-07 |
| JPS5850020B2 true JPS5850020B2 (en) | 1983-11-08 |
Family
ID=13041588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54056942A Expired JPS5850020B2 (en) | 1979-05-11 | 1979-05-11 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850020B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175088A (en) * | 1987-01-13 | 1988-07-19 | Fujimori Kogyo Kk | Film substrate for protecting synthetic resin board and protective film |
-
1979
- 1979-05-11 JP JP54056942A patent/JPS5850020B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS551190A (en) | 1980-01-07 |
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