JPS5850027B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5850027B2 JPS5850027B2 JP57077788A JP7778882A JPS5850027B2 JP S5850027 B2 JPS5850027 B2 JP S5850027B2 JP 57077788 A JP57077788 A JP 57077788A JP 7778882 A JP7778882 A JP 7778882A JP S5850027 B2 JPS5850027 B2 JP S5850027B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- ceramic
- bonded
- conductive pattern
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/581—Auxiliary members, e.g. flow barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Led Device Packages (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体電子回路、特に混成集積回路または表示
デバイス等の構成に適する電子回路用ヘラグーに関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a heat sink for electronic circuits suitable for the construction of semiconductor electronic circuits, particularly hybrid integrated circuits or display devices.
絶縁基板上に導電パターンを具え、トランジスタ、発光
ダイオード等の能動素子および抵抗、容量等の受動素子
をそれぞれ実装して混成集積回路または表示デバイス等
を構成する電子回路用ヘラグーにおいては、構造ならび
に材質上の観点から接着ロー材の流れ制御および導電パ
ターン面の保護手段とが常に問題とされて来た。Helagoo for electronic circuits, which has a conductive pattern on an insulating substrate and mounts active elements such as transistors and light emitting diodes, and passive elements such as resistors and capacitors to form hybrid integrated circuits or display devices, is characterized by its structure and materials. From the above point of view, flow control of the adhesive brazing material and means for protecting the conductive pattern surface have always been a problem.
例えば表示デバイス用へラダーでは、導電パターンの導
電面の一つに発光ダイオードの一つをロー材はスルと、
接着ロー材が接着面から浴出して導電面の余分な部分ま
で濡らす現象がよく起こり、この導電面に他の発光ダイ
オードの電極の一つをボンティング接続して両者を直列
接続しようとする企てを実質的に不可能にする問題が生
じている。For example, in a ladder for display devices, one of the light emitting diodes is placed on one of the conductive surfaces of the conductive pattern, and the brazing material is placed through it.
A phenomenon that often occurs is that the adhesive brazing material oozes out from the adhesive surface and wets the excess portion of the conductive surface, and attempts to connect the two in series by bonding one of the electrodes of another light emitting diode to this conductive surface often occur. A problem has arisen that makes it virtually impossible.
また混成集積回路用へラダーでは、導電パターン面を保
護し、抵抗値を減少させる目的で導電面に半田メッキ層
を形成することが行なわれる。Furthermore, in ladders for hybrid integrated circuits, a solder plating layer is formed on the conductive surface in order to protect the conductive pattern surface and reduce the resistance value.
この工程はボンティングの終えた半導体能動素子にはプ
レコートを施して保護したうえ半田浴に浸漬するもので
、抵抗、容量等の受動素子も同時に固着できるものであ
るが、浸漬時間が長過ぎた場合には半田材はこのプレコ
ート材と導電面との間の僅かな隙間から半導体能動素子
にまで浸漬し、ボンティング金属細線を侵蝕する現象を
おこす。In this process, the active semiconductor elements that have been bonded are protected with a precoat and then immersed in a solder bath. Passive elements such as resistors and capacitors can also be fixed at the same time, but the immersion time was too long. In some cases, the solder material soaks into the semiconductor active element through a small gap between the precoat material and the conductive surface, causing a phenomenon in which the bonding thin metal wire is corroded.
この場合にはボンティング工程上の問題は何等生じない
が半田材の流れによる別の障害が発生しており、ロー材
の流れ制御の問題は依然として残ったままである。In this case, no problem arises in the bonding process, but another obstacle occurs due to the flow of the solder material, and the problem of controlling the flow of the brazing material still remains.
このロー材の流れを制御するため従来とられて来た手段
は、高々ロー材の量、加熱温度および時間を厳格に管理
するだけであり、少し進んだものとしては導電面にきわ
めで細い巾のロー流れ防止材を塗布して所謂「せき止め
」とする方法も考えられてはいるが、熱および化学的に
防止材に適する材質が見当らず単なる提案に止まってお
り、有効な解決策となるには至っていない。The conventional means of controlling the flow of brazing material have been to strictly control the amount of brazing material, heating temperature, and time. Although it has been considered to apply a low-flow prevention material to create a so-called ``dam'', it has remained a mere proposal because no material that is thermally or chemically suitable for the prevention material has been found, and it is difficult to find an effective solution. Not yet reached.
また表面に半田メッキ層を設けて導電パターン面を保護
する方法には半田材による導電パターン材の侵蝕現象の
問題があり、材質的に必ずしも適合しているものではな
い。Furthermore, the method of protecting the conductive pattern surface by providing a solder plating layer on the surface has the problem of corrosion of the conductive pattern material by the solder material, and is not necessarily suitable in terms of materials.
導電パターン面の保護手段にはこの他厚膜混成回路にお
ける抵抗素子の保護技術をそのまま利用して導電面を樹
脂または硝子で被覆しまうとする提案がある。Another proposed means for protecting the conductive pattern surface is to cover the conductive surface with resin or glass by directly utilizing the protection technology for resistive elements in thick film hybrid circuits.
しかしながら樹脂または硝子は本来化学薬品に弱い材質
であるばかりではなく接着面積が大きい場合には導電材
との熱膨張係数差による導電材のはがれまたは保護材自
身のクラック現象を生じ易い欠点をもつものである。However, resin or glass is not only a material that is inherently susceptible to chemicals, but also has the disadvantage that if the adhesive area is large, the conductive material may peel off or the protective material itself may crack due to the difference in thermal expansion coefficient with the conductive material. It is.
これを解決するためには低膨張係数で耐薬品性をもつ保
護材を運びへラダー全面を被覆すればよいが、このよう
な性質をもつ例えば硝子は高融点材質なので導電材に反
応して抵抗値を増大させるほが、混成回路用ヘッダーの
場合には僅に周知のとおり調整済の抵抗体の抵抗値を変
動させる等の不都合な問題が生ずるので、導電面の保護
材としての材質的不適合性は細管解決されない。To solve this problem, a protective material with a low coefficient of expansion and chemical resistance can be used to cover the entire surface of the rudder, but glass, for example, has such properties and is a high melting point material, so it reacts with conductive materials and causes resistance. Increasing the value may cause disadvantageous problems such as changing the resistance value of the adjusted resistor in the case of hybrid circuit headers, as is well known, so the material may not be suitable as a protective material for the conductive surface. Gender is not tubularly resolved.
更に表示デバイスでは発光面との視覚コントラストが重
要である。Furthermore, visual contrast with the light emitting surface is important in display devices.
したがって表示デバイス用ヘッダーにはロー材の流れ制
御および導電面の保護手段の解決を中心とする製造技術
上の問題と共にこの視覚コントラストを向上するための
手段が重要な問題となり、基板材を黒色セラミックとし
たものが従来から用いられて来た。Therefore, for headers for display devices, along with manufacturing technology issues centered on solving the flow control of brazing material and protection means for conductive surfaces, the means to improve this visual contrast is an important issue, and the substrate material is made of black ceramic. has traditionally been used.
しかし仮置基板のみが黒化されたとしてもこの表面に設
けられた導電パターン自身は暗体ではないので、発光状
態にある発光ダイオードと周辺部との視覚コントラスト
は未だ十分ではあるとは言い難いものである。However, even if only the temporary substrate is blackened, the conductive pattern itself provided on this surface is not a dark body, so it is difficult to say that the visual contrast between the light emitting diode in the light emitting state and the surrounding area is still sufficient. It is something.
本発明の目的は上記半導体素子を実装する除虫ずるロー
材の流れ制御および導電面の保護手段等の製造技術上の
諸問題ならびに表示デバイスにおける視覚コントラスト
の向上に関する問題点を共に解決する電子回路用ヘッダ
ーの構造およびその製造方法を提供することである。An object of the present invention is to provide an electronic circuit which solves various manufacturing technology problems such as controlling the flow of the repellent brazing material for mounting the semiconductor element and protecting the conductive surface, as well as problems related to improving visual contrast in display devices. An object of the present invention is to provide a structure of a header for use in the present invention and a method of manufacturing the same.
本発明によればセラミック材を絶縁基板とする電子回路
用ヘッダーに形成された導電パターンの少なくとも半導
体素子を接着すべき部分とボンティングすべき部分の間
の導電面には、絶縁基板とほぼ同質のセラミック材から
なりこれと一体化に形成された絶縁層部材が被覆され、
ロー材の流れに対し2つの部分が物理的に分離された電
子回路用ヘッダーを得ることができる。According to the present invention, a conductive pattern formed on an electronic circuit header using a ceramic material as an insulating substrate has a conductive surface that is substantially the same as the insulating substrate, at least between the part where the semiconductor element is to be bonded and the part where the semiconductor element is to be bonded. An insulating layer member formed integrally with the ceramic material is coated,
It is possible to obtain an electronic circuit header in which two parts are physically separated with respect to the flow of brazing material.
本発明によればセラミック材を絶縁基板とする電子回路
用ヘッダーに形成された導電パターンの少なくとも半導
体素子を接着すべき部分とボンディングすべき部分の間
の導電面は、絶縁基板とほぼ同質の黒色セラミック材か
らなりこれと一体化に形成された絶縁層部材で被覆され
、ロー材の流れに対し2つの部分は物理的に分離される
と共に、導電パターンを含む絶縁基板全面が視覚的な暗
体に形成せしめられた電子回路用−・ラダーを得ること
ができる。According to the present invention, the conductive surface between at least the part to which the semiconductor element is to be bonded and the part to be bonded of the conductive pattern formed on the header for an electronic circuit using a ceramic material as the insulating substrate is black in color, which is almost the same as that of the insulating substrate. It is covered with an insulating layer member made of ceramic material and integrally formed with the ceramic material, and the two parts are physically separated from each other against the flow of brazing material, and the entire surface of the insulating substrate including the conductive pattern becomes a visual dark object. It is possible to obtain a ladder for electronic circuits formed in the following manner.
また本発明によれば焼結または未焼結のセラミック基板
上に設けられた導電パターンの少なくとも半導体素子を
接着すべき部分とボンディングすべき部分の間の導電面
にはセラミック基板とほぼ同質の未焼結セラミック粉末
を主成分とするペースト状セラミック材が塗布され、基
板セラミック材と一体化に焼結せしめられる電子回路用
ヘッダーの製造方法を得ることができる。Further, according to the present invention, a conductive surface of the conductive pattern provided on the sintered or unsintered ceramic substrate at least between the part to which the semiconductor element is to be bonded and the part to be bonded has a non-conductive surface having substantially the same quality as the ceramic substrate. It is possible to obtain a method for manufacturing an electronic circuit header in which a paste-like ceramic material containing sintered ceramic powder as a main component is coated and sintered integrally with a substrate ceramic material.
本発明にかかる電子回路用ヘッダーの導電パターンの少
なくとも半導体素子を接着すべき部分とボンディングす
べき部分の間の導電面には、絶縁基板とほぼ同質のセラ
ミック材からなる絶縁層部材が絶縁基板と一体化された
状態で被覆され、ロー材の流れに対し2つの部分が物理
的に分離されているので、半導体接着部分からボンディ
ング部分へのロー材の流れは完全に阻止することができ
混成集積回路または表示デバイス等の組立作業をきわめ
て容易ならしめることができる。On the conductive surface of the conductive pattern of the electronic circuit header according to the present invention, at least between the part to which the semiconductor element is to be bonded and the part to be bonded, an insulating layer member made of a ceramic material having substantially the same quality as the insulating substrate is provided. Since the two parts are coated in an integrated state and are physically separated from each other against the flow of soldering material, the flow of soldering material from the semiconductor bonding part to the bonding part can be completely blocked, thereby preventing hybrid accumulation. Assembling work of circuits, display devices, etc. can be made extremely easy.
また所謂ロー材の流れに対し「せき止め」として作用し
ている絶縁層部材は絶縁基板とほぼ同質のセラミック材
からなっているので、導電パターン面は熱的、化学的お
よび機械的にきわめて理想的に保護されるほか、導電面
のはがれ、保護部料自身のクラックなどの事故を生ずる
恐れは著しく軽減される。In addition, the insulating layer member that acts as a dam against the flow of so-called brazing material is made of a ceramic material that is almost the same as the insulating substrate, so the conductive pattern surface is extremely ideal thermally, chemically, and mechanically. In addition to this, the risk of accidents such as peeling off of the conductive surface or cracking of the protective material itself is significantly reduced.
更に上記絶縁層部材が黒色セラミック材からなり、導電
パターンを含む絶縁基板全面が視覚的暗体に形成せしめ
られたものは、発光体を載置した場合の視覚コントラス
トを著しく向上できるので表示テバイス用ヘソグーとし
て好適なものとなる。Furthermore, the insulating layer member is made of black ceramic material and the entire surface of the insulating substrate including the conductive pattern is formed into a visually dark body, which can significantly improve the visual contrast when a light emitter is mounted, making it suitable for use in display devices. It becomes suitable as belly fat.
以下図面を用いて詳細に説明する。This will be explained in detail below using the drawings.
第1図は従来の電子回路用ヘッダー上に組立てられた表
示デバイスの平面図である。FIG. 1 is a plan view of a display device assembled on a conventional header for electronic circuits.
従来の電子回路用ヘッダーは絶縁基板10表面に導電パ
ターン2が導電面3をすべて露出して形成されているの
で、発光ダイオードLED、、LED2・・・・・・・
・・・・・LEDnは表示発光パターンに従い導電面3
の上に配列されそれぞれマウントされる。In the conventional electronic circuit header, the conductive pattern 2 is formed on the surface of the insulating substrate 10 with all the conductive surfaces 3 exposed, so that the light emitting diodes LED, , LED2...
...LEDn conductive surface 3 according to the display light emission pattern
are arranged on top of each other and mounted respectively.
2つの発光ダイオードを直列に接続する必要があるとき
は、1つの発光ダイオードを接着した同一導電面に他の
発光ダイオードの電極が金属細線4を用いてボンテイン
グ接続される。When it is necessary to connect two light emitting diodes in series, the electrodes of the other light emitting diodes are bonded to the same conductive surface to which one light emitting diode is bonded using thin metal wires 4.
この際ロー材の量、加熱温度および時間等がそれぞれ適
切でないと、ロー材は接着面から溢れ出し導電面上を流
れてボンディングすべき部分までを余分に濡らしてしま
う現象がよく起きる。At this time, if the amount of brazing material, heating temperature, time, etc. are not appropriate, the brazing material often overflows from the bonding surface and flows over the conductive surface, excessively wetting the area to be bonded.
したがってロー材の量、加熱温度および時間等の接着条
件を厳格に管理できなければ爾後のボンディング接続は
不可能となる。Therefore, unless bonding conditions such as the amount of brazing material, heating temperature, and time are strictly controlled, subsequent bonding connections will be impossible.
しかしこれらの接着条件を完全に満足させる生産管理は
困難であり歩溜りの低下は避けることができない。However, production control that completely satisfies these bonding conditions is difficult, and a decrease in yield cannot be avoided.
第2図はボンディングすべき導電面までロー材が浴出し
た状態を説明する図で5は発光ダイオードLED1また
はLED2の接着面からそれぞれの導電面3上に溢れ出
たロー材を示し、発光ダイオードLED2の電極からL
ED、の接着された導電面にはボンティング接続できな
いことを表わすものである。Figure 2 is a diagram illustrating a state in which the brazing material has spilled out to the conductive surface to be bonded, and 5 shows the brazing material overflowing from the bonding surface of the light emitting diode LED1 or LED2 onto the respective conductive surface 3. L from LED2 electrode
This indicates that bonding connection cannot be made to the conductive surface to which ED is bonded.
更に従来の電子回路用ヘソグーの導電面3はすべて露出
しているので、この表面の保護手段が問題となる。Furthermore, since the conductive surface 3 of the conventional heso-goo for electronic circuits is all exposed, a method for protecting this surface becomes a problem.
表示デバイスでは通常透明樹脂または硝子で発光ダイオ
ードを含む絶縁基板の全面を被覆し、発光ダイオードと
共に導電面の表面を保護しているが、これらの保護材は
機械的にまた化学的に弱い材質であって、材質的に必ず
しも適切なものとは言い難いものであるほか、導電材ま
たは絶縁基板材との間に存在する避は難い熱膨張係数差
による導電面のはがれ現象または保護材自身のクラック
現象の発生を回避することが難しく、デバイスの信頼性
を低下せしめる要因の一つをなしているものである。In display devices, the entire surface of the insulating substrate containing the light emitting diode is usually covered with transparent resin or glass to protect the conductive surface along with the light emitting diode, but these protective materials are mechanically and chemically weak materials. However, it is difficult to say that the material is necessarily suitable, and the peeling phenomenon of the conductive surface or cracking of the protective material itself due to the unavoidable difference in thermal expansion coefficient between the conductive material or the insulating substrate material. It is difficult to avoid the occurrence of this phenomenon, and it is one of the factors that reduce the reliability of devices.
また表示デバイス個有の発光面と周辺部との視覚コント
ラストの改善は、絶縁基板材と黒化手段で目的を一応達
成されてはいるが、導電パターンは基板のほぼ全表面に
わたり形成され、その露出された導電面自身は光学的に
暗体ではなくむしろ明色体に近いものであり、しかも発
光ダイオードの周辺に比較的密度高(集中されているの
で、特に重要な発光体周辺の視覚コントラストは必ずし
も良好なものではない。Furthermore, although the objective of improving the visual contrast between the light-emitting surface and the peripheral area, which is unique to display devices, has been achieved to some extent by using insulating substrate materials and blackening means, the conductive pattern is formed over almost the entire surface of the substrate. The exposed conductive surface itself is optically not a dark body but rather a bright color body, and is relatively dense (concentrated) around the light emitting diode, so that visual contrast around the particularly important light emitter is reduced. is not necessarily good.
つぎに従来の電子回路用ヘソグーを用いて混成集積回路
を組立てるには、通常露出した導電面に所要の半導体能
動素子をそれぞれ接着して必要なボンディング接続を完
了したのち、抵抗素子および容量素子などの受動素子を
それぞれ所定のスルーホール内に挿入したうえ、半導体
能動素子にプレコート材を施し、きわめて短時間半田浴
に浸漬する。Next, in order to assemble a hybrid integrated circuit using a conventional heso-glue for electronic circuits, the required semiconductor active elements are usually adhered to the exposed conductive surface to complete the necessary bonding connections, and then resistive elements, capacitive elements, etc. Passive devices are inserted into respective through holes, and the active semiconductor devices are coated with a precoating material and immersed in a solder bath for a very short time.
この浸漬時間は決して長すぎないように十二分に管理さ
れねばならない。This soaking time must be carefully controlled so that it is never too long.
若しこの時間に長すぎるようなことがあれば、半田材は
プレコート材と導電面との間の僅かな隙間から浸透して
ボンティング金属細線を侵蝕し歩溜りを大巾に低下させ
る。If this time is too long, the solder material will penetrate through the small gap between the precoat material and the conductive surface, corrode the bonding metal wire, and greatly reduce the yield.
第3図はボンディング金属細線が浸透した半田材により
侵蝕され切断された上記混成集積回路の一部断面図を示
すもので、1,3および4はそれぞれ前回のものと同じ
く絶縁基板、導電パターン導電面およびボンティング金
属細線を、また6゜7および8はそれぞれ半導体能動素
子、プレコート材および半田材を表わすものである。Figure 3 shows a partial cross-sectional view of the above-mentioned hybrid integrated circuit which has been eroded and cut by the solder material penetrated by the thin bonding metal wires, and 1, 3 and 4 are the same as the previous one, with an insulating substrate, a conductive pattern and a conductive pattern. 6.7 and 8 represent the semiconductor active element, precoat material and solder material, respectively.
この混成集積回路の場合には半田浴に浸漬したとき、抵
抗素子および容量素子などの受動素子がそれぞれ所定の
スルーホール内に半田付けされ、同時に導電パターンの
露出した導電面には半田材がそれぞれメッキされ表面保
護材を形成すると共に、電気抵抗を軽減するよう作用す
る。In the case of this hybrid integrated circuit, when immersed in a solder bath, passive elements such as resistive elements and capacitive elements are soldered into respective predetermined through holes, and at the same time, solder material is applied to each exposed conductive surface of the conductive pattern. It is plated to form a surface protection material and also acts to reduce electrical resistance.
しかしながら半田材は導電材を侵蝕する問題があり導電
面の保護材としては樹脂および硝子と同様に材質的な適
合性を欠くものである。However, the solder material has the problem of corroding the conductive material and, like resin and glass, lacks material compatibility as a protective material for the conductive surface.
このように混成集積回路または表示デバイス等に用いら
れて来た従来の電子回路用ヘッダーは、絶縁基板の表面
に形成される導電パターンがその導電面をすべて露出さ
れたままの状態に置かれているので、接着ロー材の流れ
が十分に制御できない。In conventional electronic circuit headers used for hybrid integrated circuits or display devices, the conductive pattern formed on the surface of the insulating substrate is left with its entire conductive surface exposed. Therefore, the flow of adhesive brazing material cannot be controlled sufficiently.
また導電面を信頼性高く保護できない。あるいは表示デ
バイスの視覚コントラストを満足させることができない
等、製造技術面、信頼性および商品の付加価値面のすべ
てにわたり好ましからざる多くの問題点を有するもので
ある。Also, conductive surfaces cannot be reliably protected. Alternatively, it has many undesirable problems in terms of manufacturing technology, reliability, and added value of the product, such as not being able to satisfy the visual contrast of the display device.
本発明によればこれらの問題点は容易に解決し得る。According to the present invention, these problems can be easily solved.
第4図および第5図は本発明を表示デバイス用ヘソグー
に実施した場合の一実装例図である。FIGS. 4 and 5 are diagrams showing an example of implementation of the present invention in a display device.
本発明を実施した表示デバイス用ヘッダーは、セラミッ
ク絶縁基板1の上面が、この基板材とほぼ同質の黒色セ
ラミック材からなる絶縁基板1′で、導電パターン2の
導電面のうち発光ダイオードLED、、LED2・・・
・・・・・・・・・LEDnをそれぞれ接着すべき部分
9およびボンディングすべき部分10のみを除きほぼ全
面にわたり厚さ0501〜0.3間の層状に被覆される
。In the header for a display device according to the present invention, the upper surface of the ceramic insulating substrate 1 is an insulating substrate 1' made of a black ceramic material that is almost the same as this substrate material, and among the conductive surfaces of the conductive pattern 2, the light emitting diodes LED, . LED2...
. . . Almost the entire surface is coated in a layer with a thickness of 0.501 to 0.3, except for only the portion 9 where the LEDn is to be bonded and the portion 10 where it is to be bonded.
したがって発光ダイオードを接着すべき部分9と各ダイ
オード間をボンディング金属細線4を用いてボンティン
グ接続すべき部分10のみが露出され、これら2つの部
分の間に導電面を含む絶縁基板全面が、基板1と一体化
に形成されたこれとほぼ同質の薄いセラミック層11で
被覆されても・るので、組立に際しての発光ダイオード
の接着面9からボンティングすべき部分10への接着ロ
ー材の流れは、この間のセラミック層11で完全に阻止
できるほか、導電面は熱的、化学的および機械的に強く
、かつ基板材とは熱膨張係数をほぼ等しくする同質のセ
ラミック材で保護されるので導電面のはがれ現象または
保護材自身のクラック現象を防止することもでき、製造
技術面および信頼性向の問題点のほとんどすべては解決
される。Therefore, only the portion 9 where the light emitting diode is to be bonded and the portion 10 where each diode is to be bonded using the bonding thin metal wire 4 are exposed, and the entire surface of the insulating substrate including the conductive surface between these two portions is exposed. 1 and is coated with a thin ceramic layer 11 of substantially the same quality as this, so that the flow of the soldering material from the adhesive surface 9 of the light emitting diode to the part 10 to be bonded during assembly is reduced. , can be completely blocked by the ceramic layer 11 in between, and the conductive surface is protected by a ceramic material of the same quality that is thermally, chemically and mechanically strong and has approximately the same coefficient of thermal expansion as the substrate material. It is also possible to prevent peeling of the protective material or cracking of the protective material itself, and almost all problems in manufacturing technology and reliability are solved.
また導電パターン2はその大部分が黒色セラミック材で
被覆され従来のもののように露出されたままではないの
で発光面と周辺部との視覚コントラストを格段に改善す
ることができ、商品の付加価値向上に寄与するところは
頗る太きL−8
本発明にかかる電子回路用ヘッダーは、焼結または未焼
結のセラミック絶縁基板1に所要の導電パターン2を施
し、基板1とほぼ同質の未焼結セラミック粉末な主成分
とするペースト状セラミック材を、半導体素子を接着す
べき部分およびボンティングすべき部分の導電面のみを
除いて基板全面に塗布し、焼結温度で焼〜・て基板セラ
ミック材、ペースト状セラミック材および導電パターン
の導電面を一体化させて焼結することにより、製造する
ことができる。In addition, most of the conductive pattern 2 is covered with black ceramic material and is not exposed like in conventional patterns, so the visual contrast between the light emitting surface and the surrounding area can be significantly improved, increasing the added value of the product. The electronic circuit header according to the present invention is made by forming a required conductive pattern 2 on a sintered or unsintered ceramic insulating substrate 1, and using an unsintered A paste-like ceramic material whose main component is ceramic powder is applied to the entire surface of the substrate, except for the conductive surfaces where semiconductor elements are to be bonded and where bonding is to be performed, and then sintered at a sintering temperature to form the substrate ceramic material. , can be manufactured by integrating and sintering the paste-like ceramic material and the conductive surface of the conductive pattern.
この際ペースト状セラミック材の塗布手段は印刷技術が
有効であり、その焼結寸法は特別の場合を除き0.01
〜0.3mmK選ふのが適当である。In this case, printing technology is effective as a means of applying the paste ceramic material, and its sintered size is 0.01 except in special cases.
It is appropriate to select ~0.3 mmK.
例えば表示デバイス用ヘツグーについての具体例を示せ
ばつぎのとおりである。For example, a specific example of a display device is as follows.
厚さ1.5mmの未焼結のセラミック絶縁基板1(例え
ばAl2O3のグリーンテープ)に所定の導電パターン
2をペースト状タングステンを用いて印刷し、更にその
上にFe−Ni−Mn または特願昭47−3099
7号明細書記載のモリブデン酸塩あるいはタングステン
酸塩等の着色剤を微量に含むAl2O3粉末を主成分と
するペースト状セラミック材を、発光ダイオードを接着
すべき部分およびボンティングすべき部分の各導電面を
除いて絶縁基板全面に約40μの厚さに印刷し、160
0〜1700℃の湿式水素ガス雰囲気中でセラミックの
焼結と導電パターンのメタライジングとを完了すれば、
導電パターン2のうち発光ダイオードを接着す人き部分
およびボンティングすべき部分の導電面以外は黒色の薄
いセラミック材層で覆われた表示テバイスに適する本発
明電子回路用ヘラグーを得る。A predetermined conductive pattern 2 is printed on an unsintered ceramic insulating substrate 1 (for example, Al2O3 green tape) with a thickness of 1.5 mm using tungsten paste, and then Fe-Ni-Mn or Patent Application Showa is printed on it using tungsten paste. 47-3099
A paste-like ceramic material mainly composed of Al2O3 powder containing a small amount of a coloring agent such as molybdate or tungstate described in Specification No. Print to a thickness of about 40μ on the entire surface of the insulating substrate, excluding the surface, and
After completing the sintering of the ceramic and the metallization of the conductive pattern in a wet hydrogen gas atmosphere at 0 to 1700°C,
To obtain a heat shield for an electronic circuit according to the present invention suitable for a display device, in which the parts of the conductive pattern 2 other than the conductive surface of the part to which the light emitting diode is bonded and the part to be bonded are covered with a black thin ceramic material layer.
第6図は本発明を厚膜混成集積回路用ヘラグーに実施し
た場合の一実装断面図である。FIG. 6 is a cross-sectional view of one embodiment of the present invention applied to a thick film hybrid integrated circuit.
この場合、セラミック絶縁基板1とほぼ同質のセラミッ
ク材からなる絶縁層部材1′は、半導体素子6を接着す
べき部分およびボンディングすべき部分のほか抵抗また
は容量等の受動素子を焼き付ける部分の各導電面を除く
、絶縁基板1上にこれと一体化に形成され被覆される。In this case, the insulating layer member 1' made of a ceramic material of substantially the same quality as the ceramic insulating substrate 1 is used for each conductive part of the part where the semiconductor element 6 is to be bonded and the part to be bonded, as well as the part where passive elements such as resistors or capacitors are baked. It is formed integrally with and coated on the insulating substrate 1 except for the surface thereof.
この際絶縁層部材1′の高さを半導体素子6の高さに設
定すれば半導体素子6とボンディング金属細線4との接
触による短絡事故を防止するうえにきわめて効果的であ
る。At this time, setting the height of the insulating layer member 1' to the height of the semiconductor element 6 is extremely effective in preventing short circuit accidents due to contact between the semiconductor element 6 and the bonding thin metal wire 4.
第7図は上記本発明にかかる絶縁層部材1′が半導体素
子6とボンティング金属細線4との接触による短絡事故
の防止に有効であることを説明する図である。FIG. 7 is a diagram illustrating that the insulating layer member 1' according to the present invention is effective in preventing short-circuit accidents caused by contact between the semiconductor element 6 and the bonding thin metal wire 4.
以上詳細に説明したように本発明電子回路用ヘラグーに
よれば、導電パターンの同一導電面における半導体素子
を接着すれば部分とボンティングすべき部分との間がセ
ラミック絶縁基板と一体化された基板材とほぼ同質のセ
ラミック絶縁材で層状に被覆されているので、電子回路
の組立てに際し半導体素子の接着面からボンティング面
へのロー材の流れは完全に阻止でき製造管理を容易にな
らしめて歩溜りを飛躍的に改善するほか、導電向を基板
材とほぼ同質のセラミック材で被覆し保護しているので
、導電面のはがれおよび保護材自身のクラック現象を防
止して信頼性を格段に向上することができる。As explained in detail above, according to the electronic circuit helagoo of the present invention, when semiconductor elements on the same conductive surface of the conductive pattern are bonded, the gap between the parts to be bonded and the part to be bonded is bonded to the base integrated with the ceramic insulating substrate. Since it is coated in layers with a ceramic insulating material that is almost the same as the plate material, it can completely prevent the flow of brazing material from the bonding surface of the semiconductor element to the bonding surface when assembling electronic circuits, making manufacturing control easier and faster. In addition to dramatically improving the accumulation, the conductive direction is covered and protected with a ceramic material that is almost the same as the substrate material, which prevents peeling of the conductive surface and cracking of the protective material itself, greatly improving reliability. can do.
また被覆セラミック材は容易に黒化できるので表示テバ
イスの視覚コントラストの改善効果は顕著である。Furthermore, since the coated ceramic material can be easily blackened, the visual contrast of the display device is significantly improved.
更に本発明の実施は、表示デバイスにおける第5図の透
明なエポキシ樹脂11によるモールドまたは混成集積回
路における第6図の抵抗12に対する樹脂13による保
護材の使用を細管制限するものでないことは明らかであ
り、また外部引出しリード線14などのロー付は作業に
支障を与えるものでもない。Furthermore, it is clear that the practice of the present invention does not limit the use of the transparent epoxy resin 11 mold of FIG. 5 in a display device or the resin 13 protector for the resistor 12 of FIG. 6 in a hybrid integrated circuit. Also, brazing the external lead wire 14 does not interfere with the work.
これらロー付けを必要とする導電面には半導体素子を接
着すべき部分およびボンティングすべき部分の導電面に
対すると同様にペースト状セラミック材を塗布しないで
おけばよいことであり、製造工程において容易になし得
ることである。These conductive surfaces that require brazing need not be coated with paste ceramic material, as is the case with conductive surfaces where semiconductor elements are to be bonded and where bonding is to be performed, making it easier in the manufacturing process. It is something that can be done.
第1図は従来の電子回路用へラダー上に組立てられた表
示デバイスの平面図、第2図は従来の電子回路用ヘッダ
ーのボンディングすべき導電面までロー材が濡出した状
態を説明する図、第3図はボンティング金属細線が浸透
した半田材により侵蝕され切断された状態を説明する図
、第4図および第5図は本発明を表示デバイス用へラグ
−に実施した場合の一実装例図、第6図は本発明を厚膜
混成集積回路に実施した場合の一実装断面図、第7図は
本発明にかかる絶縁層部材が半導体素子とボンティング
金属細線との接触短絡事故防止に効果あることを説明す
る図である。
1:セラミック絶縁基板、LED:発光ダイオード、2
:導電パターン、8:半田材、3:導電パターンの導電
面、9:発光ダイオードを接着すべき導電面、4:ボン
ティング用金属細線、10;ボンディングすべき導電面
、5:浴出ロー材、11:透明エポキシ樹脂、6:半導
体素子、12:薄膜抵抗、7;プレコート材、13:薄
膜抵抗の保護用樹脂、14:外部引出しリード線。Figure 1 is a plan view of a display device assembled on a conventional ladder for electronic circuits, and Figure 2 is a diagram illustrating a state in which brazing material has wetted to the conductive surface to be bonded in a conventional header for electronic circuits. , FIG. 3 is a diagram illustrating a state in which the bonding thin metal wire is eroded and cut by the penetrated solder material, and FIGS. 4 and 5 are one implementation of the present invention when applied to a display device. An example diagram, FIG. 6 is a cross-sectional view of one implementation when the present invention is applied to a thick film hybrid integrated circuit, and FIG. 7 is a diagram showing how the insulating layer member according to the present invention prevents contact short-circuit accidents between semiconductor elements and bonding thin metal wires. It is a figure explaining that it is effective. 1: Ceramic insulating substrate, LED: Light emitting diode, 2
: conductive pattern, 8: solder material, 3: conductive surface of the conductive pattern, 9: conductive surface to which the light emitting diode is to be bonded, 4: thin metal wire for bonding, 10; conductive surface to be bonded, 5: bath-deposited brazing material , 11: transparent epoxy resin, 6: semiconductor element, 12: thin film resistor, 7: precoat material, 13: protective resin for thin film resistor, 14: external lead wire.
Claims (1)
られた導電パターンと、この導電パターンの一部に接続
された半導体素子と、前記導電パターンの他の部分に設
けられ、前記絶縁基板とほぼ同質の暗体の絶縁物質とを
含むことを特徴とする半導体装置。1. A visually dark insulating substrate, a conductive pattern provided on the insulating substrate, a semiconductor element connected to a part of the conductive pattern, and a semiconductor element connected to the other part of the conductive pattern, A semiconductor device comprising a substrate and a dark insulating material of substantially the same quality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57077788A JPS5850027B2 (en) | 1982-05-10 | 1982-05-10 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57077788A JPS5850027B2 (en) | 1982-05-10 | 1982-05-10 | semiconductor equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55045435A Division JPS5937598B2 (en) | 1980-04-07 | 1980-04-07 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57202752A JPS57202752A (en) | 1982-12-11 |
| JPS5850027B2 true JPS5850027B2 (en) | 1983-11-08 |
Family
ID=13643710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57077788A Expired JPS5850027B2 (en) | 1982-05-10 | 1982-05-10 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850027B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008290314A (en) * | 2007-05-23 | 2008-12-04 | Tokuyama Corp | Metallized substrate and manufacturing method thereof |
-
1982
- 1982-05-10 JP JP57077788A patent/JPS5850027B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008290314A (en) * | 2007-05-23 | 2008-12-04 | Tokuyama Corp | Metallized substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57202752A (en) | 1982-12-11 |
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