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JPS5937598B2 - semiconductor equipment - Google Patents
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JPS5937598B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5937598B2
JPS5937598B2 JP55045435A JP4543580A JPS5937598B2 JP S5937598 B2 JPS5937598 B2 JP S5937598B2 JP 55045435 A JP55045435 A JP 55045435A JP 4543580 A JP4543580 A JP 4543580A JP S5937598 B2 JPS5937598 B2 JP S5937598B2
Authority
JP
Japan
Prior art keywords
bonded
conductive pattern
conductive
light emitting
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55045435A
Other languages
Japanese (ja)
Other versions
JPS55146995A (en
Inventor
信造 穴沢
俊郎 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55045435A priority Critical patent/JPS5937598B2/en
Publication of JPS55146995A publication Critical patent/JPS55146995A/en
Publication of JPS5937598B2 publication Critical patent/JPS5937598B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 本発明は半導体電子回路、特に混成集積回路または表示
デバイス等の構成に適する電子回路用ヘッダーに関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a header for semiconductor electronic circuits, particularly suitable for the construction of hybrid integrated circuits or display devices.

絶縁基板上に導電パターンを具え、トランジスタ、発光
ダイオード等の能動素子および抵抗、容量等の受動素子
をそれぞれ実装して表示デバイス等を構成する電子回路
用ヘッダーにおいては、接着ロー材の流れ制御が常vc
問題とされて来た。
In headers for electronic circuits, which have a conductive pattern on an insulating substrate and mount active elements such as transistors and light emitting diodes, and passive elements such as resistors and capacitors to form display devices, etc., the flow of adhesive brazing material can be controlled. always vc
It has been considered a problem.

例えば表示デバイス用ヘッダーでは、導電パターンの導
電面の一つに発光ダイオードの一つをロー付けすると、
接着ロー材が接着面から溢出して導電面に他の発光ダイ
オードの電極の一つをボンディング接続して両者を直列
接続しようとする企てを実質的に不可能にする問題が生
じている。このロー材の流れを制御するため従来とられ
て来た手段は、高々ロー材の量、加熱温度および時間を
厳格に管理するだけであυ、少し進んたものとしては導
電面にきわめて細い巾のロー流れ防止材を塗布して所謂
「せき止め」とする方法も考えられてはいるが、単なる
提案に止まつており、有効な解決策となるには至つてい
な、・o更に表示デバイスでは発光面との視覚コントラ
ストが重要である。したがつてこの視覚コントラストを
向上するための手段が重要な問題であるが、基板材の表
面に設けられた導電パターン自身も暗体ではないので、
発光状態にある発光ダイオードと周辺部との視覚コント
ラストは未た十分であるとは言い難いものである。本発
明の目的は表示デ、・ィスにおける視覚コントラストの
向上に関する問題点を解決する電子回路用ヘッダーの構
造を提供することである。
For example, in a header for a display device, if one of the light emitting diodes is soldered to one of the conductive surfaces of the conductive pattern,
A problem has arisen in which the adhesive solder overflows from the adhesive surface, making it virtually impossible to attempt to connect the two in series by bonding one of the electrodes of another light emitting diode to the conductive surface. The conventional means of controlling the flow of brazing material are to strictly control the amount of brazing material, heating temperature, and time. Although it has been considered to apply a low flow prevention material to create a so-called ``dam'', this remains a mere proposal and has yet to become an effective solution. Visual contrast is important. Therefore, a means to improve this visual contrast is an important issue, but since the conductive pattern itself provided on the surface of the substrate material is not a dark body,
It is difficult to say that the visual contrast between the light emitting diode in the light emitting state and the surrounding area is still sufficient. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure for a header for electronic circuits that solves the problem of improving visual contrast in display devices.

本発明によれば、絶縁性基板と、この絶縁性基板上に配
設され、半導体表示素子が取υ付けられた第1の導電パ
ターンと、この絶縁性基板上に配設され、一端が半導体
表示素子の電極に接続されたボンディング線の他端が接
続された第2の導電パターンと、半導体表示素子と前記
ボンディング線の前記他端が接続され/て位置との間に
設けられかつ前記ボンディング線の下に延在された視覚
的に暗体の絶縁物層とを含む半導体装置を得る。本発明
によれば、視覚的に暗体の絶縁物層を半導体表示素子近
傍に有することとなるので、半導体表示素子が発光した
時の視覚コントラストが著しく向上できるので表示デバ
イス用ヘツダ一として好適なものである。更に絶縁物層
はいわゆるロー材のせき止め効果も果すことができるの
で、ロー材が半導体表示素子部からあふれ出して、ボン
デイング部をおおつてしまい、ボンデイングができなく
なるというような欠点が解消される。更に絶縁物層を導
電パターンと重なるように形成すると、導電パターンの
はがれ等を防ぐ保護効果も果すことができる。以下、図
面を用いて本発明をより詳細に説明する。
According to the present invention, there is provided an insulating substrate, a first conductive pattern disposed on the insulating substrate and having a semiconductor display element attached thereto, and a first conductive pattern disposed on the insulating substrate and having one end connected to the semiconductor display element. a second conductive pattern to which the other end of the bonding line connected to the electrode of the display element is connected; and a position where the other end of the bonding line is connected to the semiconductor display element; and a visually dark insulator layer extending below the lines. According to the present invention, since a visually dark insulating layer is provided near the semiconductor display element, the visual contrast when the semiconductor display element emits light can be significantly improved, making it suitable as a header for a display device. It is something. Furthermore, the insulating layer can also have the effect of damming up the brazing material, which eliminates the problem that the brazing material overflows from the semiconductor display element section and covers the bonding section, making it impossible to perform bonding. Furthermore, by forming the insulating layer so as to overlap the conductive pattern, a protective effect can be achieved to prevent the conductive pattern from peeling off. Hereinafter, the present invention will be explained in more detail using the drawings.

第1図は従来の電子回路用ヘツダ一上に組立てられた表
示デバイスの平面図である。
FIG. 1 is a plan view of a display device assembled on a conventional electronic circuit header.

従来の電子回路用ヘツダ一は絶縁基板1の表面に導電パ
ターンλが導電面3をすべて露出して形成されているの
で、発光ダイオードLEDl,LED2,LEDnは表
示発光″ゞターンに従い導電面3の上に配列されそれぞ
れマウントされる。2つの発光ダイオードを直列に接続
する必要があるときは、1つの発光ダイオードを接着し
た同一導電面に他の発光ダイオードの電極が金属細線4
を用いてポンデイング接続される。
In the conventional electronic circuit header 1, the conductive pattern λ is formed on the surface of the insulating substrate 1 with the entire conductive surface 3 exposed, so that the light emitting diodes LEDl, LED2, LEDn follow the display light emission'' turn. When it is necessary to connect two light emitting diodes in series, the electrodes of the other light emitting diodes are connected to the same conductive surface to which one light emitting diode is bonded.
Connected using ponding.

この際ロー材の量、加熱温度および時間等がそれぞれ適
切でないと、口ー材は接着面から溢れ出し導電面上を流
れてボンデイングすべき部分までを余分に濡らしてしま
う現象がよく起きる。したがつてロー材の量、加熱温度
および時間等の接着条件を厳格に管理できなければ爾後
のボンデイング接続は不可能となる。しかしこれらの接
着条件を完全に満足させる生産管理は困難であり歩溜り
の低下は避けることができない。第2図はボンデイング
すべぎ導電面までロー材が溢出した状態を説明する図で
5は発光ダイオードLEDLまたはLED2の接着面か
らそれぞれの導電面3上に溢れ出たロー材を示し、発光
ダイオードLED2の電極からLEDlの接着された導
電面にはボンデイング接続できないことを表わすもので
ある。更に従来の電子回路用ヘツダ一の導電面3はすべ
て露出してお9、その露出された導電面自身は光学的に
暗体ではなくむしろ明色体に近いものであり、しかも発
光ダイオードの周辺に比較的密度庫く集中されているの
で、特に重要な発光体周辺の視覚コントラストは必ずし
も良好なものではない。このように表示デバイス等に用
いられて来た従来の電子回路用ヘツダ一は、絶縁基板の
表面に形成される導電パターンがその導電面をすべて露
出されたままの状態に置かれているので、接着ロー材の
流れが十分に制御できない。
At this time, if the amount of brazing material, heating temperature, time, etc. are not appropriate, the brazing material often overflows from the bonding surface and flows over the conductive surface, wetting the area to be bonded. Therefore, unless bonding conditions such as the amount of brazing material, heating temperature, and time are strictly controlled, subsequent bonding will be impossible. However, production control that completely satisfies these bonding conditions is difficult, and a decrease in yield cannot be avoided. Fig. 2 is a diagram illustrating the state in which the brazing material overflows to the conductive surface of the bonding joint, and 5 shows the brazing material overflowing from the bonding surface of the light emitting diode LEDL or LED2 onto the respective conductive surface 3. This indicates that bonding connection cannot be made from the electrode to the conductive surface to which the LED 1 is bonded. Furthermore, all of the conductive surfaces 3 of conventional headers for electronic circuits are exposed 9, and the exposed conductive surfaces themselves are not optically dark bodies but are rather close to bright bodies, and moreover, the area around the light emitting diode The visual contrast around the particularly important light emitters is not necessarily good because the light emitters are relatively densely concentrated. In the conventional header for electronic circuits that has been used in display devices and the like, the conductive pattern formed on the surface of the insulating substrate is placed in a state where the conductive surface is completely exposed. The flow of adhesive brazing material cannot be controlled sufficiently.

また導電面を信頼性高く保護できない。あるいは表示デ
バイスの視覚コントラストを満足させることができない
等、製造技術面、信頼性訃よび商品の付加価値面のすべ
てにわたジ好ましからざる多くの問題点を有するもので
ある。本発明によればこれら問題点は容易に解決し得る
。第3図は本発明を表示用デバイス用ヘツダ一に実施し
た場合の一実施例図である。
Also, conductive surfaces cannot be reliably protected. Alternatively, it has many undesirable problems in terms of manufacturing technology, reliability, and added value of the product, such as not being able to satisfy the visual contrast of the display device. According to the present invention, these problems can be easily solved. FIG. 3 is a diagram showing an embodiment of the present invention applied to a header for a display device.

本発明を実施した表示デバイス用ヘツダ一は、セラミツ
ク絶縁基板1の上面が、この基板材とほぼ同質の黒色セ
ラミツク材からなる絶縁部材Vで、導電パターン2の導
電面のうち発光ダイオードLEDl,LED2・・・L
EDをそれぞれ接着すべき部分9およびホンnデイング
すべき部分10のみを除きほぼ全面にわた沙厚さ0.0
1〜0.3m77!の層状に被覆される。
In the display device header 1 according to the present invention, the upper surface of the ceramic insulating substrate 1 is an insulating member V made of a black ceramic material that is almost the same as the substrate material, and the light emitting diodes LED1 and LED2 are connected to the conductive surface of the conductive pattern 2. ...L
Thickness: 0.0 over almost the entire surface, except only for the part 9 where the ED is to be bonded and the part 10 which is to be bonded.
1~0.3m77! covered in layers.

したがつて発光ダイオードを接着すべき部分9と各ダイ
オード間をボンデイング金属細線4を用いてボンデイン
グ接続すべき部分10のみが露出され、これら2つの部
分の間の導電面を含む絶縁基板全面が、基板1と一体化
に形成されたこれとほぼ同質の薄いセラミツク層Vで被
覆されているので、組立に際しての発光ダイオードの接
着面9からボンデイングすべき部分10への接着ロー材
の流れは、この間のセラミツク層1′で完全に阻止でき
るほか、導電面は熱的、化学的および機械的に強く、か
つ基板材とは熱膨脹係数をほぼ等しくする同質のセラミ
ツク材で保護されるので導電面のはがれ現象または保護
材自身のクラツク現象を防止することもでき、製造技術
面および信頼性面の問題点のほとんどすべては解決され
る。また導電パターン2はその大部分が黒色セラミツク
材で被覆され従来のもののように露出されたままではな
いので発光面と周辺部との視覚コントラストを格段に改
善することができ、商品の付加価値向上に寄与するとこ
ろは頗る人きい。本発明にかかる電子回路用ヘツダ一は
、焼結または未暁結のセラミツク絶縁基板1に所要の導
電パターン2を施し、基板1とほぼ同質の未焼結セラミ
ツク粉末を主成分とするペースト状セラミツク材を、半
導体素子を接着すべき部分卦よびボンデイングすべき部
分の導電面のみを除いて基板全面に塗布し、焼結温度で
焼いて基板セラミツク材、ペースト状セラミツク材訃よ
び導電パターンの導電面を一体化させて焼結することに
より、製造することができる。
Therefore, only the portion 9 where the light emitting diode is to be bonded and the portion 10 where each diode is to be bonded using the bonding metal thin wire 4 are exposed, and the entire surface of the insulating substrate including the conductive surface between these two portions is exposed. Since it is coated with a thin ceramic layer V formed integrally with the substrate 1 and having substantially the same quality as the substrate 1, the flow of the adhesive brazing material from the adhesive surface 9 of the light emitting diode to the part 10 to be bonded during assembly is limited during this time. In addition, the conductive surface is protected by a ceramic material of the same quality that is thermally, chemically, and mechanically strong and has approximately the same coefficient of thermal expansion as the substrate material, so peeling of the conductive surface is prevented. It is also possible to prevent the cracking phenomenon or the cracking phenomenon of the protective material itself, and almost all problems in terms of manufacturing technology and reliability are solved. In addition, most of the conductive pattern 2 is covered with black ceramic material and is not exposed like in conventional patterns, so the visual contrast between the light emitting surface and the surrounding area can be significantly improved, increasing the added value of the product. I like people who contribute to this. The electronic circuit header 1 according to the present invention is made by applying a required conductive pattern 2 to a sintered or unsintered ceramic insulating substrate 1, and then forming a paste-like ceramic material whose main component is unsintered ceramic powder having substantially the same quality as the substrate 1. is applied to the entire surface of the substrate, excluding only the conductive surface of the part where the semiconductor element is to be bonded and the part to be bonded, and baked at a sintering temperature to coat the ceramic material of the substrate, the paste-like ceramic material, and the conductive surface of the conductive pattern. It can be manufactured by integrating and sintering.

この際ペースト状セラミツク材の塗布手段は印刷技術が
有効であり、その焼結寸法は特別の場合は除き0.01
〜0.3m77!に選ぶのが適当である。例えば表示デ
バイス用ヘツダ一についての具体例を示せばつぎのとお
9である。厚さ1.5m1Lの未焼結のセラミツク絶縁
基板1(例えばAl2O3のグリーンテープ)上に所定
の導電パターン2をペースト状タングステンを用いて印
刷し、更にその上にFe−Ni−Mnまたは特願昭47
−30997号明細書記載のモリブデン酸塩あるいはタ
ングステン酸塩等の着色剤を微量に含むAl2O3粉末
を主成分とするペースト状セラミツク材を、発光ダイオ
ードを接着すべき部分卦よびボンデイングすべき部分の
各導電面を除いて絶縁基板全面に約40μの厚さに印刷
し、1600〜1700℃の湿式水素ガス雰囲気中でセ
ラミツクの焼結と導電パターンのメタライジングとを完
了すれば、導電パターン2のうち発光ダイオードを接着
すべき部分およびボンデイングすべき部分の導電面以外
は黒色の薄いセラミツク材層で覆われた表示デバイスに
適する本発明電子回路用ヘツダ一を得る。第4図訃よび
第5図は上記本発明にかかる絶縁層部材Vが半導体素子
6とボンデイング金属細線4との接触による短絡事故の
防止に有効であることを説明する図である。
In this case, printing technology is effective as a means of applying the paste ceramic material, and its sintered size is 0.01 except in special cases.
~0.3m77! It is appropriate to choose. For example, a specific example of a header for a display device is as follows. A predetermined conductive pattern 2 is printed on an unsintered ceramic insulating substrate 1 (for example, Al2O3 green tape) with a thickness of 1.5 ml using tungsten paste, and then Fe-Ni-Mn or a patent application pattern is printed on it using tungsten paste. Showa 47
A paste-like ceramic material mainly composed of Al2O3 powder containing a small amount of a coloring agent such as a molybdate or a tungstate described in the specification of No. 30997 was applied to each of the parts to which the light emitting diode was to be bonded and the parts to be bonded. If the entire surface of the insulating substrate, excluding the conductive surface, is printed to a thickness of approximately 40 μm, and the ceramic sintering and metallization of the conductive pattern are completed in a wet hydrogen gas atmosphere at 1600 to 1700°C, the conductive pattern 2 A header for an electronic circuit according to the present invention suitable for a display device is obtained, which is covered with a thin black ceramic material layer except for the conductive surface of the part to which the light emitting diode is to be bonded and the part to be bonded. FIG. 4 and FIG. 5 are diagrams for explaining that the insulating layer member V according to the present invention is effective in preventing short-circuit accidents caused by contact between the semiconductor element 6 and the bonding thin metal wire 4.

この場合、第4図はセラミツク絶縁基板1とほぼ同質の
セラミツク材からなる絶縁層部材Vは、半導体素子6を
接着すべき部分}よびボンデイングすべき部分のほか抵
抗12または容量等の受動素子を形成する部分の各導電
面を除く、絶縁基板1上にこれと一体化に形成され被覆
される。
In this case, FIG. 4 shows that an insulating layer member V made of a ceramic material of substantially the same quality as the ceramic insulating substrate 1 has a portion to which a semiconductor element 6 is to be bonded and a portion to be bonded, as well as passive elements such as a resistor 12 or a capacitor. It is formed integrally with and coated on the insulating substrate 1 except for each conductive surface of the portion to be formed.

この際第5図のように絶縁層部材Vの高さを半導体素子
6の高さに設定すれば半導体素子6とボンデイング金属
細線4との接触による短絡事故を防止するうえにより一
層効果的である。以上詳細に説明したように本発明電子
回路用ヘフツダ一によれば、半導体素子を接着すべき部
分とボンデイングすべき部分との間がセラミツク絶縁基
板と一体化された基板材とほぼ同質のセラミツク絶縁材
で層状に被覆されているので、電子回路の組立てに際し
半導体素子の接着面からボンデイング面へのロー材の流
れは完全に阻止でき製造管理を容易にならしめて歩溜り
を飛躍的に改善するほか、導電面を基板材とほぼ同質の
セラミツク材で被覆し保護しているので、導電面のはが
れお・よひ保護材自身のクラツク現象を防止して信頼性
を格段に向上することができる。
At this time, if the height of the insulating layer member V is set to the height of the semiconductor element 6 as shown in FIG. 5, it is more effective in preventing short circuit accidents due to contact between the semiconductor element 6 and the bonding thin metal wire 4. . As described in detail above, according to the header for electronic circuits of the present invention, the gap between the part to which the semiconductor element is to be bonded and the part to be bonded is made of ceramic insulation of substantially the same quality as the substrate material integrated with the ceramic insulating substrate. Since the material is coated in layers, the flow of brazing material from the bonding surface of the semiconductor element to the bonding surface can be completely prevented when assembling electronic circuits, making manufacturing management easier and dramatically improving yield. Since the conductive surface is covered and protected with a ceramic material that is substantially the same as the substrate material, it is possible to prevent peeling of the conductive surface and cracking of the protective material itself, thereby significantly improving reliability.

また被覆セラミツク材は容易に黒化できるので表示デバ
イスの視覚コントラストの改善効果は顕著である。その
上被覆セラミツクは半導体表示デバイスの高さと同じに
なされているのでボンデイング線がたれ下つても表示デ
バイスと接触するようなことはない。更に本発明の実施
は、表示デバイスにおける第4図の透明なエポキシ樹脂
によるモールド工程に対する樹脂13による保護材の使
用を何等制限するものでないことは明らかであり、また
外部引出しリード線14などのロー付け作業に支障を与
えるものでもない。これらロー付けを必要とする導電面
には半導体素子を接着すべき部分卦よびボンディングす
べき部分の導電面に対すると同様にペースト状セラミツ
ク材を塗布しないでおけばよいことであり、製造工程に
訃いて容易になし得ることである。
Furthermore, since the coated ceramic material can be easily blackened, the visual contrast of the display device is significantly improved. Moreover, since the ceramic coating is made to be at the same height as the semiconductor display device, even if the bonding line hangs down, it will not come into contact with the display device. Furthermore, it is clear that the practice of the present invention does not limit the use of the protective material of the resin 13 in the molding process of the transparent epoxy resin shown in FIG. It does not interfere with the installation work. As with the conductive surfaces of the parts to which semiconductor elements are to be bonded and the parts to be bonded, it is sufficient to avoid applying paste-like ceramic material to these conductive surfaces that require brazing, which may cause problems in the manufacturing process. This can easily be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電子回路用ヘツダ一上に組立てられた表
示デバイスの平面図、第2図は従来の電子回路用ヘツダ
一のボンデイングすべき導電面までロー材が溢出した状
態を説明する図、第3図は本発明を表示デバイス用ヘツ
ダ一に実施した場合の一実施例図、第4図}よひ第5図
は本発明にかかる絶縁層部材が半導体素子とボンデイン
グ金属細線との接触短絡事故防止に効果あることを説明
する図である。 1・・・・・・セラミツク絶縁基板、LED・・・・・
・発光ダイオード、2・・・・・・導電パターン、8・
・・・・・半田材、3・・・・・・導電パターンの導電
面、9・・・・・・発光ダイオードを接着すべき導電面
、4・・・・・・ボンデイング用金属細線、10・・・
・・・ボンデイングすべき導電面、5・・・・・・溢出
口ー材、6・・・・・・半導体素子、12・・・・・・
薄膜抵抗、7・・・・・・プレコート材、13・・・・
・・薄膜抵)保護用樹脂、14・・・・・・外部引出し
リード線。
Fig. 1 is a plan view of a display device assembled on a conventional header for electronic circuits, and Fig. 2 is a diagram illustrating a state in which brazing material overflows to the conductive surface to be bonded of the conventional header for electronic circuits. , FIG. 3 shows an embodiment of the invention applied to a header for a display device, FIG. It is a figure explaining that it is effective in preventing a short circuit accident. 1... Ceramic insulating substrate, LED...
・Light emitting diode, 2... Conductive pattern, 8.
... Solder material, 3 ... Conductive surface of conductive pattern, 9 ... Conductive surface to which the light emitting diode is to be bonded, 4 ... Thin metal wire for bonding, 10 ...
... Conductive surface to be bonded, 5 ... Overflow port material, 6 ... Semiconductor element, 12 ...
Thin film resistor, 7... Precoat material, 13...
... Thin film resistor) protective resin, 14... External lead wire.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁性基板と、この絶縁性基板上に配設され、半導
体表示素子が取り付けられた第1の導電パターンと、前
記絶縁性基板上に配設され、一端が前記半導体表示素子
の電極に接続されたボンディング線の他端が接続された
第2の導電パターンと、前記半導体表示素子と前記ボン
ディング線の前記他端が接続された位置との間に設けら
れ、かつ前記ボンディング線の下に延在された視覚的に
暗体の絶縁物層とを含むことを特徴とする半導体装置。
1 an insulating substrate, a first conductive pattern disposed on the insulating substrate and having a semiconductor display element attached thereto, and a first conductive pattern disposed on the insulating substrate and having one end connected to an electrode of the semiconductor display element; a second conductive pattern to which the other end of the bonding line is connected, and a position where the other end of the bonding line is connected to the semiconductor display element, and extending below the bonding line. 1. A semiconductor device comprising: a visually dark insulating layer;
JP55045435A 1980-04-07 1980-04-07 semiconductor equipment Expired JPS5937598B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55045435A JPS5937598B2 (en) 1980-04-07 1980-04-07 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55045435A JPS5937598B2 (en) 1980-04-07 1980-04-07 semiconductor equipment

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP57077787A Division JPS57202751A (en) 1982-05-10 1982-05-10 Semiconductor device
JP57077788A Division JPS5850027B2 (en) 1982-05-10 1982-05-10 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS55146995A JPS55146995A (en) 1980-11-15
JPS5937598B2 true JPS5937598B2 (en) 1984-09-11

Family

ID=12719226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55045435A Expired JPS5937598B2 (en) 1980-04-07 1980-04-07 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5937598B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0744021Y2 (en) * 1987-06-05 1995-10-09 京セラ株式会社 Package for storing semiconductor devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748869B2 (en) * 1972-02-23 1982-10-19

Also Published As

Publication number Publication date
JPS55146995A (en) 1980-11-15

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