JPS5854415B2 - Information processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing method for increasing the utilization efficiency of a buffer storage device.

It has been put into practical use to provide a buffer storage device between a central processing unit that operates at high speed and a peripheral device that operates at low speed to increase the operating efficiency of both devices.

For example, when a printing device is used as a peripheral device, by temporarily storing the printing information to be printed in a buffer storage device, the central processing unit can use the information to obtain the printing information regardless of the printing speed of the printing device. Processing can be performed sequentially at high speed.

However, in recent years, the number of types of control signals that control the operation of printing devices has tended to increase dramatically in order to improve the degree of freedom for users. It has become difficult to construct control signals for

For this reason, conventionally, control signals of a type that cannot be expressed with the same number of bits as the number of bits that constitute the print information of a character (hereinafter referred to as specific control signals) are transmitted via a buffer storage device. Either the code system is directly supplied to the printing device and the control signals obtained from the buffer storage device are completely different from the code system, or the information stored in the buffer storage device has a variable length structure, and the print information and all control signals are Methods such as storing the information in a buffer storage device have been adopted.

However, in the former method, the buffer storage device fully performs its function during the period when no specific control signal exists, but when the specific control signal is interposed between print information,
While the printing device does not receive the specific control signal, printing information that is controlled by this specific control signal cannot be input to the buffer storage device, and after the printing device receives the specific control signal, it cannot receive the printing information that is controlled by this specific control signal. Buffer storage devices are restricted by specific control signals, such as inputting print information into the buffer storage device, and cannot fully perform their functions.

Furthermore, when the storage information in the buffer storage device has a variable length configuration, it is necessary to insert a redundant code, such as a delimiter code, for each piece of storage information, which reduces the usage efficiency of the buffer storage device and reduces the capacity of the buffer storage device. The control circuit also becomes complicated.

The present invention has been made in view of these points, and even if the types of control signals for peripheral devices increase, print information and all control signals can be stored in a buffer storage device without adding special redundant codes. The present invention provides an information processing method that can increase the utilization efficiency of a buffer storage device by storing data in a buffer storage device.

An embodiment of the present invention will be described below with reference to the drawings.

Reference numeral 1 denotes a program section. This program section 1 stores programs necessary for various information processing, and further supplies program signals generated by the programs to the calculation section 2 in sequence.

The program section 1 includes a storage device for storing programs, a control device for inputting and outputting information to and from the storage device, and a program control device for sequentially reading out the program step by step and performing step jump operations as necessary. etc.

The arithmetic unit 2 performs various information processing operations based on program signals supplied from the program unit 1, and includes various arithmetic registers and their control circuits, an arithmetic circuit that performs four arithmetic operations and logical operations, and a judgment unit that performs various judgments. It is composed of circuits, etc.

The arithmetic unit 2 supplies control signals generated by the information processing operation to the program unit 1, and also supplies information signals to be printed out of the results of the information processing operation to the output buffer unit 3.

In the program section 1 and the arithmetic section 2, program commands, control signals, information to be subjected to arithmetic processing, etc. all have a 7-bit structure.

The information signal to be printed, which is supplied from the calculation section 2 to the output buffer section 3, has a structure of 8 bits per digit, with the processing result of the calculation section 2 being stored in the 1st to 7th bits, and 0 in the 8th bit. It has a bit configuration in which (binary number) is written.

Reference numeral 4 denotes a specific command detection unit, and this specific command detection unit 4 is sequentially given program signals supplied from the program unit 1 to the calculation unit 2, and among these program signals, control signals for the printing unit 8, which will be described later, For example, it detects a start signal, tab control signal, skip signal, stop signal, etc., and supplies these control signals to the output buffer section 3 in an 8-bit configuration.

The bit configuration of this control signal is such that the first to seventh bits are the control signal to control the printing section 8, and the eighth bit is the "control signal".
1” (binary number) is written.

The output buffer section 3 stores the information signal to be printed obtained from the calculation section 2 and the control signal for the printing section 8 obtained from the specific command detection section 4 in an 8-bit configuration in the order in which they were output. It is configured.

The program section 1, calculation section 2, and output buffer section 3 constitute a part of a central processing unit.

Reference numeral 5 denotes a judgment unit, which is supplied with the output signal for each digit from the output buffer unit 3, and judges whether the output signal is an information signal or a control signal. It is determined whether the 8th bit of the signal is "0" or "1.".

The signal for which the eighth bit of one digit is determined to be O'' by the determining section 5, that is, the information signal to be printed, is supplied to the parity generating section 6.

The parity generating section 6 writes a check bit for parity check into the information signal obtained through the determining section 5 at the eighth bit position.

Further, the signal for which the eighth bit is determined to be "1" by the determining section 5, that is, the control signal, is supplied to the decoder section 7, and the decoder section 7 converts this control signal into a certain standardized code system. The conversion is performed to create a command signal, and the timing at which the command signal is output is adjusted.

Reference numeral 8 denotes a printing section, and this printing section 8 is configured to check the parity of the information signal obtained through the parity generation section 6, and if it is correct, print this information signal based on the command signal supplied from the decoder section I. has been done.

On the other hand, when an error is detected by the parity check of the interspace section 8, an error detection signal is given to the program section 1, which instructs the start address of the error routine of the program section 1.

The determination section 5, parity generation section 6, and decoder section 7 constitute part of an input/output control device that controls the interface between the central processing unit and the printing section 8.

According to the above configuration, for the information signal obtained from the arithmetic unit 2, the 8th bit is "0".
1" is written in the 8th bit for the control signal obtained from the output buffer section 3 and stored in series in the output buffer section 3.

The determination unit 5 determines whether the eighth bit of each signal outputted from the output buffer unit 3 is “0” or “1”, thereby dividing the signal into an information signal and a control signal again.

Thereafter, the information signal is supplied to the printing section 8 with a parity bit written therein by the parity generating section 6, and the control signal is subjected to appropriate code conversion in the decoder section 7 and then supplied to the printing section 8.

For example, when what the calculation unit 2 reads from the program unit 1 is a command word, that is, a control signal, the control signal is written to the output buffer 3, and the specific command detection unit 4 detects that it is a control signal. , "1" is added to the 8th bit of the control signal.

This results in 8 bits and is output to the determining section 5, where the 8th bit is checked.

Since it is a control signal, it is output to the decoder 7, and the printing section is controlled by this control signal.

Next, when the control signal exceeds 7 bits, for example, 10 bits, the output buffer 3 first stores the 7 bits of the control signal and the discrimination information "1'", then the remaining 3 bits and the discrimination information "1". Write ″.

These control signals are sequentially outputted to the printing unit 8 via the judgment unit 5 and decoder 7, and one control signal (10 bits) is output.
Thus, the printing unit 8 is controlled.

Further, a print information signal, which is data such as a numerical value calculated by the calculation section 2, is written to the output buffer 3 in 7 bits in the same manner as the control signal.

Then, "0" is added to the 8th bit of this information.

Since 8 bits of this print information are "0" in the judgment section 5, it is judged to be print information, and the parity generation section 6 performs a parity check and a parity bit is added to make it 8 bits.

When the 7 bits of print information and the parity bit are output to the print section 8, the print section 8 again creates a parity bit from the 7 bits of the received print information and compares it with the received parity bit.

If both of the compared parity pits match, it is determined to be normal, and the normal printing information is printed.

Further, if there is a mismatch, the printing unit 8 determines that there is an error, and outputs an error signal to the program unit 1.

Therefore, discrimination information for distinguishing between the information signal to be printed and the control signal for controlling the printing section 8 is written in the 8th bit of each, and the information signal and the control signal are serially sent to the output buffer section 3. This is stored and separated into an information signal and a control signal by the judgment unit 5, and then the information signal is
Since the parity bit is written in the bit th position and the information signal is supplied to the printing unit 3, the types of control signals that can be stored in the output buffer unit 3 are dramatically increased.
Discrimination information for distinguishing between information signals and control signals is written in the parity pit position (8th bit) of the information signal, so the number of bits that make up one digit does not increase, and the output buffer section 3 can be used effectively. It is possible.

In the above embodiments, the peripheral device has been described as a printing device, but the present invention is not limited to this, and can be applied to paper tape punching/reading devices, magnetic tape storage devices, magnetic disk devices, etc. in the same way. Of course you can get it.

Furthermore, each circuit block portion can be modified in various ways without departing from the spirit of the invention, such as by using arbitrary electronic elements to take on various circuit configurations.

As described in detail above, since the discrimination information for distinguishing between an information signal and a control signal is written in the parity bit position of the information signal, both signals can be serially stored in the buffer storage device. The variety of control signals that the buffer storage can store increases dramatically, and since no special bit positions are required for redundancy codes, the buffer storage can be used very efficiently and, as a result, the central processing The waiting time of the device can be reduced and the processing efficiency can be improved.

[Brief explanation of drawings]

The drawing is a block diagram showing an embodiment of the present invention. 1...Program section, 2...Calculation section,
3...Output buffer section, 4...Specific instruction detection section, 5...Judgment section, 8...Printing section.

Claims (1)

[Claims] 1. In an information processing system that stores information in a buffer storage device interposed between a central processing unit and a peripheral device, an information signal obtained as a processing result of the central processing unit and a control that instructs the control of the peripheral device. storage means for adding and writing distinguishing information for distinguishing the two signals into each parity bit position of the signal, and storing the information signal and the control signal sequentially and serially in the buffer storage device; and an output from the storage means. a determining means for determining from information whether the discrimination information is the information signal or the control signal; a decoding means for decoding the control signal determined by the determination and outputting it to the peripheral device; An information processing system comprising: parity generating means for creating a parity pit from the determined information signal, adding it to the information signal, and outputting it to a peripheral device.