JPS5854511B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a field effect transistor having a vertical structure.

A typical bipolar type high frequency, high power transistor has a large number of emitters formed in a stripe pattern to achieve high power, but bipolar transistors are prone to thermal runaway and it is difficult to increase the power of the device.

On the other hand, field effect transistors with a vertical structure do not suffer from thermal runaway and are suitable for high power devices.

Conventional field effect transistors with a vertical structure include a buried gate structure with a cross-sectional structure as shown in Figure 1, or a diffusion gate with a cross-sectional structure as shown in Figure 2 in which the gate is deeply diffused and a channel is formed between the gates. structures are manufactured.

Referring to FIG. 1, a gate 1 is manufactured by diffusing impurities into a semiconductor substrate 2 in the form of a mesh and then forming a semiconductor layer 3 by epitaxial growth.

If an attempt is made to narrow the gate spacing in order to increase the frequency, the gates will expand due to auto-doping and diffusion during epitaxial growth and will no longer form a channel, so the gate spacing cannot be made very narrow.

Further, since the gate resistance is large, this structure is useful as a low frequency high power device, but is not suitable for high frequency applications.

On the other hand, the diffusion gate structure shown in FIG. 2 has a large junction capacitance because the gate 4 is formed by diffusion.

In addition, since the distance between the gates is approximately several μ, the gate
It is difficult to take out the source electrodes so that the sources 5 are not short-circuited.

However, since a metal electrode can be placed over the gate, it is more suitable for high-frequency applications than the buried gate method, but since the gate portion occupies most of the area of the device, this structure is still suitable for high-power applications for high-frequency applications. Not suitable for elements.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a vertical field effect transistor using a self-alignment method, which improves the drawbacks of the conventional vertical field effect transistor and enables high frequency and large power.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained in detail below with reference to the drawings.

Referring to FIG. 3, reference numeral 11 is an As-doped (100) N-type silicon substrate having a specific resistance of 0.005Ω.

12 is an epitaxial layer of 8Ω·c on one main surface of the substrate.
It was formed into an N type layer with a layer thickness of 6 μm and had a specific resistance of rn, and was obtained by reducing 5iCt4 with hydrogen at 1150°C.

Next, by diffusing 1μ of boron, a P-type diffusion layer 1
3 was formed.

Next, 1000 silicon oxide films (SiO2 films)14.
A silicon nitride film (Si3N4 film) 15 having a thickness of 1000 mm was sequentially laminated.

Next, as shown in FIG. 4, the silicon nitride film button and the silicon oxide film in the portion that would become the source region were etched away in a predetermined pattern using a well-known photolithography technique.

At this time, the direction of the striped source region pattern was shifted by 45° from the tangent to (111) as shown in FIG.

This is because the later etching rate of the alkaline etching solution decreases in the order of (211) > (100) > (111), and it is difficult to obtain an inverted trapezoidal structure if the pattern direction is tangential to (111). It's for a reason.

Note that in FIG. 10, S indicates a source region, and L indicates a tangent to the (111) plane.

Next, using the silicon nitride film and silicon oxide film as masks, phosphorus was diffused to form a diffusion layer 16 (FIG. 5).

At this time, the diffusion is performed deeper than the diffusion layer 13 that has already been formed.

Next, the surface of the semiconductor substrate was selectively thermally oxidized at 1000° C. to form an oxide film 17 (FIG. 5) with a thickness of 600A.

Next, the silicon nitride film and silicon oxide film that formed the mask are removed, resulting in a structure as shown in FIG.

Next, as shown in FIG. 11, the P-type diffusion layer 13 was selectively removed by applying a voltage of 2 cm to the back surface of the substrate 11 in a 5N solution of KOH at 80° C. with the back surface of the substrate 11 being positive and the platinum electrode 18 being negative. .

At this time, the N-type layer is passivated and protected and is not etched.

The etching depth is 1.2μ, and the cross section has an inverted trapezoidal structure.

Next, as shown in FIG. 6, using the silicon oxide film 16 as a mask, 5×10 15 boron/Ca ions were implanted to form a gate region 19.

Boron is injected only into the lower part of the hole.

Next, as shown in FIG. 7, after removing the silicon oxide film 17, the entire surface of the substrate is oxidized at 1000°C, and the silicon oxide layer 2
A zoooi was formed.

Next, as shown in FIG. 8, the silicon oxide film 20 is etched by ion etching using Ar gas in the direction perpendicular to the substrate.
The horizontal part was removed.

Among them, the silicon oxide film 20'&'! on the side wall portion is removed by the above-mentioned etching. A woman who is being etched.

Next, a source electrode 21 and a gate electrode 22 were formed by sequential electron beam evaporation of aluminum at 300 OA, chromium at 2 OA, and copper at 5 OA.

At this time, these electrodes are patterned in self-alignment with the source and gate portions to form an inverted trapezoidal structure.

Copper was evaporated to facilitate subsequent plating.

The source islands are far apart and need to be connected.

For this reason, gold plating was then applied at an applied voltage of 1.2 .

Since the voltage applied to the gate layer is lower than that of the source layer by the junction voltage, plating is performed only on the source electrode.

The thickness of the plated gold layer 23 is 20μ, which is sufficiently large compared to the spacing between the sources of 0.8μ, so that the sources are interconnected.

Next, the silicon piece 24 of the n+ common electrode plate having an area corresponding to the entire source region and the gold layer 23 are bonded together by thermocompression bonding, as shown in FIG. 9.

The gold layer 23 and the silicon piece 24 were effective in lowering the thermal resistance of the device.

Next, a source, a gate, and a drain electrode were attached to the substrate to form a device.

According to the above-mentioned manufacturing method of the present invention, since only one mask is required for photoetching, there is no need to consider pitch deviation buttons and misalignment when manufacturing the mask, and a mask with a very high density pattern can be manufactured. It has the distinct advantage that it can be used and easily fabricated into high-frequency, high-power devices.

[Brief explanation of the drawing]

1 and 2 are sectional views showing a conventional field effect transistor.
0 and 11 are diagrams for explaining the above-mentioned embodiment of the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts, respectively. 11...N-type silicon substrate, 12...Epitaxial layer, 13...P-type diffusion layer, 14.17...Silicon oxide film, 15...Silicon nitride film, 16...Diffusion layer , 20.20... silicon oxide film, 23... gold layer, 24... silicon piece (common electrode plate).

Claims (1)

[Claims] 1. A step of diffusing and forming a second conductivity type region on one main surface of a (100) semiconductor substrate of the first conductivity type, and a step of shifting the second conductivity type region by 45° from the tangent direction to (111) on the surface of the second conductivity type region. forming a first thin layer having a plurality of patterned openings formed in the same direction; and using the thin layer as a mask, diffusion is performed through these openings into the semiconductor substrate to form a first conductivity type diffusion layer. a step of providing a second thin layer as a mask of the first thin layer and etching away the first thin layer; selecting a second conductivity type layer using the second thin layer as a mask; forming a second conductivity type layer by ion implantation in the etched area by etching the first conductivity type diffusion layer loosely, and removing the second thin layer and forming an oxide film on the entire surface. After forming the first conductivity type diffusion layer and the second conductivity type layer, the oxide film on the upper surface thereof is subjected to ion etching to form an exposed surface, and a common electrode is formed with respect to the metal electrode on the upper surface of each of the first conductivity type diffusion layers. A method for manufacturing a semiconductor device, comprising the step of electrically connecting plates.