JPS5855670B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a field effect transistor having a vertical structure.

Conventional bipolar type high frequency, high power transistors have a large number of emitters arranged in striped form to achieve high power output, but bipolar type transistors are prone to thermal runaway, making it difficult to increase the power output of the device.

On the other hand, field effect transistors with a vertical structure do not suffer from thermal runaway and are suitable for high-power devices.

Conventional field effect transistors with a vertical structure include a buried gate structure with a cross-sectional structure as shown in Figure 1, or a diffusion gate with a cross-sectional structure as shown in Figure 2 in which the gate is deeply diffused and a channel is formed between the gates. structures are manufactured.

In FIG. 1, a gate 1 is manufactured by diffusing impurities into a semiconductor substrate 2 in a mesh-like manner and then forming a semiconductor layer 3 by evixaxial elongation.

If an attempt is made to narrow the gate spacing in order to increase the frequency, the gates will expand due to autodoping and diffusion during evixaxial growth and will no longer form a channel, so the gate spacing cannot be made very narrow.

Furthermore, since the gate resistance is large, this structure is useful as a low frequency high power device, but is not suitable for high frequency L).

On the other hand, the diffusion gate structure shown in FIG. 2 has a large junction capacitance because the gate 4 is formed by diffusion.

Furthermore, since the distance between the gates is on the order of several 1, it is difficult to take out the source electrodes so as not to short-circuit between the gates and the sources 5.

However, because metal electrodes can be placed on the gate, this structure is more suitable for high-frequency applications than the buried gate method. Not suitable for power devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a vertical field effect transistor using a self-alignment method, which improves the drawbacks of the conventional vertical field effect transistor and enables high frequency and high power.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained in detail in the order of steps with reference to the drawings.

In Figure 3, 11 has a specific resistance of 0.0150・snoring (i
oo) P-type silicon substrate, 12 is a P-type epitaxial layer with a thickness of 10 ll and having a resistivity of 15Ω·α.

Next, a polycrystalline silicon layer 13 having a thickness of 15 μm was formed on the epitaxial layer by thermal decomposition of monosilane.

Next, the silicon layer 13 was thermally oxidized to form a silicon oxide film 14 with a thickness of 1,000 layers, and a silicon nitride film 15 with a thickness of 100 layers was further laminated.

(Hereinafter, the silicon oxide film will be referred to as an oxide film, and the silicon nitride film will be referred to as a nitride film.) Next, as shown in FIG. is removed by etching with NI(,F).

At this time, the striped source region (S in Fig. 9)
) pattern is tangential to the (111) plane (the 9th
Adjusted to L) in the figure.

Next, using the nitride film 15 and the oxide film 14 as masks, poron is diffused into the polycrystalline silicon layer until the impurity concentration is 1. , 5
A diffusion layer 16 of 1020 pieces/cc was formed.

At this time, since the diffusion coefficient of the polycrystalline silicon layer is faster than that of the single crystal layer, almost no boron is diffused into the epitaxial layer 12.

Next, selective oxidation was performed using the nitride film 15 and the oxide film 14 as masks, and an oxide film 17 was formed at 1000° C. to a thickness of 4000 μm.

Next, the nitride film 15 and the oxide film 14 are removed, and then the first
The polycrystalline silicon layer was etched in a 5N solution of KOH as shown in FIG.

At this time, the diffusion layer is hardly etched by the etching solution.

Also, the grooves are inverted trapezoidal.

After etching in the above solution, the epitaxial layer was etched by 2 μm.
After etching, it becomes as shown in FIG.

Note that at this time, the side surface makes an angle of 547 degrees with the (100) plane.

Next, as shown in FIG. 6, using the oxide film 11 as a mask, 5XIO''/d ions of phosphorus were implanted to form a gate region 18.

Next, the oxide film was removed and the entire surface of the substrate was oxidized at 100°C to form a new oxide film with a thickness of 2,000. The horizontal portions are removed, leaving an unetched oxide film 19 on the side surfaces, as shown in FIG.

Next, a source electrode 20 and a gate electrode 21 were formed by sequential electron beam evaporation of 3000 λ of aluminum, 200 λ of chromium, and 500 λ of copper.

At this time, these electrodes are patterned in self-alignment with the source and gate portions to form an inverted trapezoidal structure.

Copper was later deposited to facilitate plating.

The source islands are far apart and need to be connected.

For this reason, gold plating was then applied at an applied voltage of 1.2V.

Since the junction voltage development force r4 pressure of the gate layer is lower than that of the source layer, plating is performed only on the source electrode.

The thickness of the entire layer 22 is 20μ, and the spacing between the sources is 0.8
Since it is sufficiently large compared to μ, the sources are interconnected.

Next, n+ silicon pieces 23 and 22 having an area corresponding to the entire source region are bonded together by thermocompression bonding to form a structure as shown in FIG.

22 and silicon piece 23 were effective in lowering the thermal resistance of the device.

Next, a drain electrode was attached to the substrate to form a device.

According to the above manufacturing method of the present invention, only one mask is required for photoetching, and there is no need to consider pitch misalignment and misalignment when manufacturing the mask, and a mask with a very high density pattern can be produced. It has the distinct advantage that it can be used and easily fabricated into high-frequency, high-power devices.

[Brief explanation of drawings]

1 and 2 are both cross-sectional views showing a conventional field effect transistor. FIGS.
Figures 1 and 10 are diagrams for explaining the present invention in detail. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 11... Silicon substrate, 13... Polycrystalline silicon layer, 14... Silicon oxide film, 15
... Silicon nitride film, 16 ... Diffusion layer, 18 ... Gate region, 17.19 ...
・Silicon oxide III, 20...source electrode,
21...gate electrode, 23... silicon piece (common electrode plate).

Claims (1)

[Claims] 1 a step of forming a polycrystalline semiconductor layer or a semiconductor layer obtained by anodizing this substrate on the main surface of a semiconductor substrate of a first conductivity type; a step of forming a thin layer, and performing diffusion through the semiconductor layer through the opening using the thin layer as a mask;
The process of forming a conductive type diffusion layer and providing a second thin layer using the first thin layer as a mask involves removing the first thin layer and etching beyond the semiconductor layer to form a first conductive type diffusion layer. A step of forming a second conductivity type layer by ion implantation after the etching, and a step of forming a first conductivity type diffusion layer after removing the second thin layer and forming an oxide film on the entire surface. a step of performing ion etching on the oxide film on the top of the second conductivity type layer to form an exposed surface; a step of forming a metal electrode on each of the exposed surfaces by vapor deposition; and a step of forming a metal electrode on the top surface of each of the first conductivity type diffusion layers. A method for manufacturing a semiconductor device, comprising the step of electrically connecting a common electrode plate to an electrode.