JPS5855526B2 - buffer memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory, particularly a speed matching buffer memory used in an interframe encoding system.

In devices that use variable length codes, such as interframe coding systems, it is necessary to use a buffer memory to match the transmission line speed.

Ideally, this buffer memory stores the transmission sequence (0), but in this case, problems may arise in writing and reading speeds.

For example, assume that there is an encoder that generates output at sample intervals, and that the output is variable-length coded and transmitted.

In this case, if the code length is 1 bit, the sample interval is 1
All you have to do is write bit by bit to the buffer memory, which is not difficult if the sampling frequency is low.

However, when the code length is 10 bits to 20 bits, 1/10 r, ... or 1/2 of the sample interval.
Writing must be done with 0, which causes a problem because the required processing speed is too fast.

Corresponding to the method of serially writing the input series to the buffer memory, a method of writing the information of each sample in parallel is known.This method has many advantages in terms of processing speed, but If a parallel writing method is used when handling codes, there is a problem in that the amount of hardware increases.

The present invention solves the problems of the conventional methods as described above, and the buffer memory storage capacity is calculated for the transmission sequence itself and used for various controls. The purpose is to provide a method for storing data by exchanging it to another code format rather than in the form of a transmission sequence, thereby increasing the processing speed and simplifying the hardware of the computer memory. It is said that

FIG. 1 shows the configuration of an embodiment of the present invention, and the circuit includes an input terminal 1
, an output terminal 2, a storage capacity calculation circuit 3, a data storage circuit 4, a data conversion circuit 5, and a data reconversion circuit 6.

In this embodiment, it is assumed that the input data from the encoder is a number from 0 to 7, and that the format of the output data to the transmission line and the accumulated data is the format shown in FIG.

The octal digits input to the input terminal 1 are supplied to the data conversion circuit 5, where they are converted into 3-bit fixed length binary codes.

At the same time, the code length when this signal is converted into a transmission line code format (code length of a variable length code, for example, code length 7 when the input is 96") is determined and sent to the storage amount calculation circuit 3. .

The 3-bit fixed length code created by the data conversion circuit 5 is sent to the data storage circuit 4 and stored therein.

At the same time, the memory amount calculation circuit 3 adds the code length at that time.

On the other hand, on the output side of the data storage circuit 4, a data reconversion circuit 6
A 3-bit fixed length signal is supplied each time there is a request from the data reconversion circuit 6, and the data reconversion circuit 6 converts this signal into a variable length code and sends it to the transmission line.

At the same time, the code length is sent to the storage amount calculation circuit 3 and subtracted from the storage amount.

Note that the reason why the storage amount calculation circuit 3 calculates the storage amount in the above description can be considered to be based on the following reason.

That is, as is clear from FIG. 2, each time data is input from the input terminal 1, 3-bit fixed length data is supplied from the data conversion circuit 5 to the data storage circuit 4.

In this manner, the amount of data stored in the data storage circuit 4 increases by three bits each time data is input.

By the way, each 3-bit value of the accumulated data corresponds to the length of the variable length code sent from the output terminal 2 by adding 1 to the numerical value "X" expressed in binary code format. There is.

That is, the relationship between the code length of accumulated data and the code length of effective data that the code signifies is as follows.

Code length of accumulated data Effective data code length 1110"
) 3 bits 16"+1+7 bits On the other hand, the 3-bit data read from the data storage circuit 4 is converted by the data reconversion circuit 6 into a variable length code having a length of "X"+1.

After all of this "X"+1 bit data is sent to the output terminal 2, the next 3-bit fixed length data is read out from the data storage circuit 4.

As is clear from the above explanation, how many bits (effective data storage amount) of the amount of data to be actually sent to the transmission path is stored in the data storage circuit 4 is calculated by accumulating 3 bits each of the fixed length code. It cannot be expressed with a value.

The storage amount calculation circuit 3 is a circuit that calculates the storage amount of this effective data, and each time 3-bit data is written to the data storage circuit 4, the code length represented by that data is
+1 is added to the amount of storage up to that point, and each time 3-bit data is read out from the data storage circuit 4, the code length "Xo"+1 represented by that data is subtracted from the amount of storage up to that point.

Normally, the amount of read data and the amount of written data in a buffer memory are different, and if the amount of written data is significantly larger, there is a risk that the buffer memory will overflow.

In order to prevent this overflow, the amount of information generated can be reduced by controlling the encoding circuit connected to the front stage of the buffer memory, such as a predictive encoding circuit such as a pre-value DPCM for video, and stopping encoding every other sample. suppress.

Furthermore, if the amount of written data is significantly smaller, there is a risk that the buffer memory will underflow.

To prevent underflow, the original signal itself can be written into a buffer memory, for example by compressing the band using an encoding circuit.

Normal buffer memory overflow and underflow control is performed by monitoring the effective data storage amount and determining whether the storage amount exceeds a predetermined threshold.

However, when storing in a fixed length code format as in the embodiment of the present invention, as described above, the data storage circuit 4
The amount of data accumulated in , and the amount of storage calculated by the storage amount calculation circuit 3 are different.

Therefore, even if the calculation result in the storage amount calculation circuit 3 is not in an overflow or underflow mode, the storage amount in the data storage circuit 4 may overflow or underflow.

In this case, regardless of the memory capacity of the memory capacity calculation circuit 3,
It is necessary to forcibly control the encoding circuit connected to the previous stage.

By storing in this format, the storage amount in the storage amount calculation circuit 3 is calculated in the transmission line code format, but since the actual storage in the data storage circuit 4 is performed in a 3-bit fixed length code, A margin can be given to the reading speed, and the hardware configuration is extremely easy.

When adopting the configuration shown in FIG. 1, there is a certain statistical ratio between the amount of storage in the storage amount calculation circuit 3 and the amount actually stored in the data storage circuit 4. should be maintained, but if long codes are consecutive, the amount of storage will be large and the number of bits stored in the data storage circuit 4 will be small, and vice versa, the amount of storage will be A situation may occur in which only the number of bits stored in the data storage circuit 4 increases even though the data size is not increased much.

Normally, various controls are performed based on the storage capacity of the storage capacity calculation circuit 3.

On the other hand, since the capacity of the data storage circuit 4 is finite, even if the data storage circuit 4 is about to be filled with data, there is a situation where the storage capacity is small and the state is set to allow data input. .

In order to avoid such difficulties, as described above, the amount of storage in the data storage circuit 4 is supplied to the storage amount calculation circuit 3, and when the amount of storage reaches a predetermined amount, the amount of storage calculation is calculated based on the value at that time. Even if the value is small, the control is made to maximize it.

Conversely, a situation may occur in which the storage amount shows a large value even though the storage amount in the data storage circuit 4 is small.

For this reason, when the storage amount becomes less than a certain value, information is given to the storage amount calculation circuit 3, and control is performed to set the storage amount to a small value.

By employing the storage system and control system as described above, it is possible to obtain a buffer memory that provides sufficient processing speed and has a simple hardware configuration.

Although the code format shown in FIG. 2 is used in this embodiment, it is obvious that code formats other than this can be applied to the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows a code format in the embodiment shown in FIG. In the figure, 1 is an input terminal, 2 is an output terminal, 3 is a storage amount calculation circuit, 4 is a data storage circuit, 5 is a data conversion circuit, and 6 is a data reconversion circuit.

Claims (1)

[Claims] 1. When the information generation speed and the information transmission speed are different, in a buffer memory for matching them, a storage amount calculation circuit that calculates the storage amount in a transmission code format, and a storage amount calculation circuit that calculates the storage amount in a transmission code format, and a storage amount calculation circuit that calculates the storage amount in a transmission code format when the information generation speed and information transmission speed are different. 1. A buffer memory comprising a data storage circuit for performing speed matching processing control using the storage amount calculation circuit.