JPS5855530B2 - Bidirectional bus parity check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity check method for a bidirectional bus that makes it possible to easily identify in which part an error occurring during data transfer is caused.

In parity operations on traditional data buses.

Separate parity checkers/generators were provided for the bus-in and bus-out lines, and they performed bus-in parity checks and bus-out parity generation.

Furthermore, in order to diagnose the data bus, driver/receiver, and data buffer, data had to be transferred between devices.

The present invention is based on the above considerations, and is capable of performing parity check in the case of reception and generation of parity in the case of transmission with a single parity checker/generator. The object of the present invention is to provide a bidirectional bus parity check method that allows device self-diagnosis without data transfer.

Therefore, the bidirectional bus parity check method of the present invention is capable of transmitting information other than a parity code to the data line in a device that exchanges information with other devices via a bidirectional bus having a data line and a parity line. A transmitting means for transmitting data, a receiving means for receiving information on the data line, a calculating means for calculating a predetermined parity from the transmitted information or received information, and a parity code of the transmitted information inputted to the transmitting means and a parity code generated by the calculating means. In the case of reception, the received information on the data line and the received parity code on the parity line are input to the calculation means, and a parity check is performed by the calculation means before transmission. In this case, a parity bit is calculated and created from the transmission information on the data line, and the comparison means compares the created parity code with the parity code of the transmission information inputted to the transmission means. It is characterized by the fact that

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 shows a data flow in the case of reception according to one embodiment of the present invention.
BLOCK DIAGRAM OF AN EMBODIMENT FIG. 2 is a block diagram of one embodiment of the present invention showing data flow in the case of transmission.

1 and 2, 1 is a driver, 2 is a receiver, 3 is a buffer, 4 is a parity checker/generator, 5 is a multiplexer, 6 is a flip-flop, 7
is an inverting circuit, 8 is a driver, 9 is a receiver, 10 is an exclusive OR circuit or EOR circuit, 11 is an AND circuit,
BD indicates a pure data bit line, and BP indicates a parity bit line.

Note that the diagonally shaded bus line and thick solid line indicate data flow.

The bidirectional bus consists of a pure data bit line BD and a parity bit line BP, and the pure data bits are, for example, 8
It's bit.

FIG. 1 illustrates the case of reception, in which the drive gate signal is logic rOJ.

Therefore, the information on the pure data bit line BD and the parity bit on the parity bit line BP are
The signal is input to a checker/generator 4, where a parity check is performed.

The result of the parity check is sent to flip-flop 6 via multiplexer 5, and flip-flop 6 is set when a parity error is detected.

FIG. 2 illustrates the case of transmission, in which the drive gate signal is a logic "1".

Therefore, the transmission information in the buffer 3 is sent out by the driver 1 onto the pure data bit line BD.

The transmitted information on the pure data bit line BD is input to the parity checker/generator 4 via the receiver 2, and the parity bits created by the parity checker/generator 4 are sent out on the parity bit line BP. be done.

The parity checker/parity bits generated by generator 4 and the parity bits in buffer 3 are E
It is input to an OR circuit 10, and the output of the EOR circuit 10 is sent to a flip-flop 6 via a multiplexer 5.

When the FOR circuit 10 outputs a logic "1", the flip-flop processor is set.

For example, when a failure occurs in the pure data bit line BD, in the driver 1, in the receiver 2, or in the buffer 3, the EOR circuit 10 outputs logic "1".

As is clear from the above description, according to the present invention, it is possible to perform self-diagnosis of devices without data transfer between devices.

[Brief explanation of drawings]

FIG. 1 shows a data flow in the case of reception according to one embodiment of the present invention.
BLOCK DIAGRAM OF AN EMBODIMENT FIG. 2 is a block diagram of one embodiment of the present invention showing data flow in the case of transmission. 1...driver, 2...receiver, 3
... Buffer, 4 ... Parity checker/generator, 5 ... Multiplexer,
6...Flip-flop, 7...NOT circuit, 8...Driver, 9...Receiver, 10...EOR circuit, 11・・・・・・
AND circuit, BD...Pure data bit line, B
P...Parity bit line.

Claims (1)

[Claims] 1. In a device that sends and receives information to and from other devices via a bidirectional bus having a data line and a parity line, a sending unit that sends transmission information other than a parity code to the data line, and a receiving unit that receives information on the data line. , calculation means for calculating a predetermined parity from the transmitted information or received information;
and a comparison means for comparing the parity code of the transmission information input to the transmission means and the parity code generated by the calculation means, and in the case of reception, the reception information on the data line and the reception information on the parity line are installed. The parity code is input to the above-mentioned calculation means to perform a parity check, and in the case of transmission, the parity bit is calculated and created from the transmission information on the data line, and the created parity code and the above-mentioned transmission A parity check method for a bidirectional bus, characterized in that the comparing means compares a parity code of transmission information inputted to the means.