JPS5855753B2 - Cycloconverter gate pulse supply method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cycloconverter in which separately excited converters each consisting of a plurality of cycloconductors are connected in anti-parallel relationship to each other to supply a current of variable polarity to a load, and particularly relates to The present invention relates to a method for supplying gate pulses to individual thyristors constituting a converter.

FIG. 1 is a schematic configuration diagram showing an example of a conventional cycloconverter configured with a separately excited thyristor converter.

In the same figure, separately excited thyristor converters AI and A2 each include six thyristors U1 to 3-phase bridge connected.
Z1. Consisting of U2 to Z2, these are the power supply vR, vs
, are connected in parallel to each other with respect to the VT, and are connected in anti-parallel with each other to the load to form a cycloconverter.

In such a cycloconverter, regardless of the polarity of the output voltage ■, converter A1 must supply the load current when the load current i>0, and converter A2 must supply the load current when i (0). The converter is required to perform an inverse conversion operation for a period of time.

The inverse conversion operation can be carried out by operating the converter as a separately excited inverse converter, which enables operation of a load with an arbitrary power factor and regeneration of electric power.

FIG. 2 is a waveform diagram showing the basic operation when a cycloconverter is operated with a general inductive load.

As is clear from the figure, regardless of the polarity of the output voltage V, when the load current i is positive, that is, during the period tp, the converter A1 is activated, and when the load current i is negative, that is, during the period tn. Converter A2 operates.

Furthermore, each converter operates as a forward converter during periods tpr and tnr, and as an inverse converter during periods tpi and tni.

One method of operating these converters is to use an electrical changeover circuit SW, as implied in FIG.

In other words, the polarity of the load current command value i is determined by the polarity determining circuit P.
After confirming that the load current i has become zero, select either converter A1 or A2 with the changeover switch SW after a predetermined time period, that is, after a current stop period. do it.

If this is done, there will be no circulating current, and therefore a reactor for suppressing circulating current will be unnecessary, so the device can be made more compact, but on the other hand, control before and after the current stop period will be complicated.

On the other hand, the output voltage or output current of the cycloconverter is controlled by the individual thyristors U1 to Z1. It can be controlled by the firing phase or control angle with respect to the power supply voltage of U2 to Z2.

The ignition pulse or gate pulse for determining such a phase or control angle is, in FIG.
(not shown) from a common gate control circuit G which receives and receives control inputs.

By the way, the load for such a cycloconverter includes relatively light inductive loads such as ordinary electric motors.
Strong inductive loads such as linear motors may also be used.

In such a case, a fast current rise is required to increase the output frequency of the cycloconverter and obtain a good sinusoidal waveform.

In other words, as the output frequency increases, the inductive reactance increases, so the current does not rise smoothly. Therefore, at the moment when the sinusoidal output current starts flowing, a large output voltage close to the converter's full capacity is required. will be done.

However, if the conventional gate pulse supply method is adopted, the converter may not be able to output the maximum output voltage at the time of polarity change when the load current is switched.

This point will be explained in more detail below.

FIG. 3 is a block diagram showing a conventional gate pulse supply system, and FIG. 4 a = d are timing waveform diagrams for explaining the operation.

In FIG. 3, only the gate pulse supply circuit for the converter (2) is shown, but it is assumed that the other converters are similarly provided.

In this case elements 1, 2, 3, 4 can be shared for both transducers.

In addition, in the figure, only a part of the AND gate of the other converter is shown, and the others are omitted.

At this point, the current regulator 1 calculates the current value l1st of the load current (corresponding to i in FIG. 1).

) and target value l5oll (corresponds to i% in FIG. 1).

) is used to output an adjustment output so that the comparison result is zero.

The output of this regulator 1 is given to the firing angle adjustment unit 2 as a phase control signal, so the firing angle adjustment unit 2 compares this phase control signal with a synchronization signal separately generated from the power supply voltage and matches it. At this point, a flip-flop (not shown) that outputs 120°el (electrical angle) is operated to obtain a pulse of a predetermined width, which is taken out via an AND circuit 51 and sent to each separately excited converter A. Supply to the gate of Cyrisk.

Note that the gate pulse is given to the upper group thyristors U, V, W and the lower group thyristors x, y, z in pairs, and the thyristors in these pairs are 12 times apart from each other.
It has a phase difference of CP chu.

Further, the pulse shaping circuit 3 is provided for superimposing a high frequency pulse on the constant pulse obtained from the firing angle adjustment unit 2 to obtain a comb-shaped pulse.

This is to prevent the iron core from being saturated when a gate pulse is applied via a pulse transformer, and may be omitted in some cases.

The current switching command circuit 4 corresponds to the polarity discrimination circuit P shown in FIG. 1, and controls two cyrisk converters A1. Only one of A2 is selectively operated.

Note that 11 is a polarity switch.

On the other hand, since the output from the current switching command circuit 4 is given to the AND circuit 5, at the moment when the current switching command is given, a predetermined si risk determined by that timing becomes conductive. In this case, as mentioned above, the converter is not necessarily capable of outputting the maximum output voltage.

For example, at the time of releasing the pulse off in Fig. 4, that is, at the time "to" immediately after the current stop period provided at the time of switching the output current has elapsed, the control signal C makes the control angle α as small as possible so that the output voltage rises quickly. , that is, αmin. However, at the timing shown in Figure 4, the control signal C intersects with the synchronization signal u''-z at W and y, so the gate pulse is given to the thyristor W. and Y
As a result, the output waveform is as shown with horizontal lines in FIG. 4d.

Therefore, the output voltage P at the time of pulse-off cancellation to
It can be seen that o is not the maximum voltage □ that can be output at that time.

This invention was made in view of the above, and its purpose is to
To provide a gate pulse supply system capable of outputting the output voltage of a converter up to the full capacity of the converter when changing the polarity of a load current when a highly inductive load is being carried.

According to the present invention, the above object is to supply a load current of variable polarity to a load by connecting at least two separately excited syrisk converters each consisting of 6 syrisks connected in a 3-phase bridge in an anti-parallel relationship with each other. In the gate pulse supply method of the cycloconverter, when the polarity of the load current changes, not only the predetermined thyrisk that should be driven at that time, but also the thyrisk that is driven with a phase delay of 1200 el (electrical angle) from the predetermined thyrisk. This is achieved by supplying a gate pulse to both.

In other words, the sirisk to be driven when the pulse off is released is determined by the control signal and synchronization signal at that time, and as mentioned above, the converter may not be able to output the maximum voltage at that time. Considering that the separately excited converter is driven with a delayed phase and its output characteristics,
The phase control circuit is constructed by focusing on the fact that the maximum output voltage can always be obtained by driving the sirisk of the phase delayed by at least 12 CP.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 6 is an explanatory diagram for explaining the operation in FIG. 5, and FIG.
The figure is a waveform diagram showing the operation of FIG. 5.

What is shown in FIG. 5 is an execution determination circuit 6, a monostable multi
, AND circuits 8, 9, and an OR circuit 10, this differs from that shown in FIG. 3, so this point will be mainly explained below.

Current regulator 1, firing angle regulator 2 and pulse shaping circuit 3
The gate pulse created by is outputted through an OR circuit 10 and an AND circuit 5, and is also configured to be outputted through an AND circuit 9.

In this case, the AND circuit belonging to thyristor V is given a gate pulse for firing thyristor U, and the AND circuit belonging to thyristor Y is given a gate pulse for firing thyristor X. The same applies hereafter.

In other words, the upper sirisk groups U and V. W and two of each of the lower side risk groups x, y, and z are operable.

Moreover, when driving thyristors U and Y, the next phase, such as thyristors V and Z, which is delayed by 120°ell, is driven by 1 at the same time.

On the other hand, an AND circuit 8 is connected to the other input side of the AND circuit 9, and an execution determination circuit 6 and a monostable multi 7 are connected to the input side of the AND circuit 8, respectively.

The execution determination circuit 6 detects, for example, that the output frequency has exceeded a predetermined value and sends a signal to the AND circuit 8. The monostable multi 7 receives a command from the current switching command circuit 4 and outputs a signal to the AND circuit 8. It operates for a time tm (see Figure 7),
A signal is given to the AND circuit 8.

Therefore, for example, when a gate pulse is given to fire the thyristors W and Y, if an execution command is given from the execution determination circuit 6 and a switching command is given from the current switching command circuit 4, the thyristor W Not only are the AND circuits 9 and 5 belonging to thyristors U and Z opened, but also AND circuits 9 and 5 belonging to thyristors U and Z, which are delayed in phase by 1200 degrees, are also opened.

This point will be further explained with reference to FIGS. 6 and 7.

The one shown in FIG. 7 is exactly the same as the one shown in FIG. 4 with respect to conditions such as the power supply voltage, control signal, synchronization signal, and pulse-off release time, so the power supply voltage and b shown in FIG. 4 are exactly the same. The relationship with the control signal shown in is omitted.

As is clear from FIG. 7, the pulse-off release point to
However, in this invention, the thyristors U and Z, which are 120 degrees behind the thyristors W and Y, are also operated by applying a gate pulse.

This relationship is shown in FIG. 7a, and is drawn out and shown with diagonal lines to emphasize that it is provided additionally.

FIG. 6 is for explaining the above relationship from another perspective, and shows the phase (indicated by a circle) that should operate at the time of to.

), the above-mentioned additional pulse is applied to the phase delayed by 120°el indicated by the arrow.

In this way, with respect to the normal phase risk that should be driven at the time of release of the pulse-off, the normal phase is 1200
By also operating the phase risk of el delay,
An output voltage having characteristics as shown by hatching in FIG. 7C is obtained.

In this way, no matter what time the switch is made, the maximum output voltage at that time will always be obtained from the converter.

Although the above explanation deals with the case where no circulating current flows through the converter, it can be similarly applied when circulating current flows, and the same applies not only when switching the load current but also at startup. It can be applied in various ways.

In addition, when this invention is applied, if the output frequency is low, it may cause a problem, so the execution determination circuit is of a frequency discrimination type that operates at a frequency higher than the frequency. It may be possible to operate under the following conditions.

Further, although the above description has been made regarding the case where the configuration is made using only separately excited converters, the present invention can be similarly applied to the case where a reactive power compensation type cycloconverter is configured in conjunction with a self-excited converter.

As described above, according to the present invention, in a gate pulse supply method of a cycloconverter that connects separately excited converters made of a plurality of cycloconverters in an antiparallel relationship with each other to supply a load current of variable polarity to a load, When changing the polarity of the current, the polarity of the load current can be changed by simply applying a gate pulse not only to the predetermined sirisk that should be driven at that time, but also to the sirisk that is driven with a phase delay of 120°eO from the predetermined sirisk. At the time of conversion, the maximum output voltage that can be output from the converter at that time can be easily obtained.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram showing an example of a conventional cycloconvert constructed from a separately excited cycloconverter, and Figure 2 is a diagram showing the voltage and current characteristics when the cycloconvert is operated with an inductive load. FIG. 3 is a block diagram showing a conventional gate pulse supply method, FIG. 4 is a timing diagram for explaining the operation of FIG. 3, and FIG.
FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG. 6 is an explanatory diagram for explaining the main operation of FIG. 5, and FIG. 7 is a timing diagram for explaining the operation of FIG. 5. Explanation of symbols, U1 to Z1. U2~Z2; Cyrisk, Al
2 A2 z separately excited Sirisk converter, G; gate control circuit, P; polarity discrimination circuit, 1; current regulator, 2; firing angle adjustment unit, 3; pulse shaping circuit, 4; current switching finger◆
Circuit, 5L52, 8, 9: AND circuit, 6: Execution determination circuit, 7: Monostable multi, 10: OR circuit, 11: Polarity switching circuit.

Claims (1)

[Claims:] A cycloconverter in which at least two separately excited converters made of 13-phase bridge-connected thyrisks are connected in antiparallel relation to each other, and are capable of supplying a load current of variable polarity to a load. , a current switching command circuit that selectively operates only one of the converters in accordance with each polarity of the load current, and one of the converters selected based on a command from the current switching command circuit. In a gate pulse supply method for a cycloconverter, the cycloconverter has a phase control circuit that supplies a gate pulse at a control angle according to a control signal each time to each constituent thyrisk, and a gate for a predetermined pair of thyrisks output from the phase control circuit. A logic circuit is provided that can supply pulses to other thyrisk pairs that are in a phase relationship with a delay of 120°e1 from the predetermined thyrisk pair, and is driven at that time when the polarity of the load current changes. By simultaneously applying gate pulses to a normal thyristor pair and another thyristor pair having a phase relationship 120°el behind the normal thyristor pair, the converter obtains the maximum output voltage that can be output at that time. A gate pulse supply method for a cycloconverter, which is characterized by: 2. In the gate pulse supply method for a cycloconverter according to claim 1, the input of the logic circuit receives at least the gate pulse output from the phase control circuit and the output of the current switching command circuit. 1. A gate pulse supply method for a cycloconverter, characterized in that the gate pulse supply method is configured such that a pulse output from a means that operates for a certain period of time is provided.