JPS5856970B2 - Processing method for semiconductor devices with nitride film - Google Patents

Description

Detailed Description of the Invention The present invention relates to a semiconductor device having a nitride film, for example, a so-called MNO3 (Metal-Nitride-Ox) in which a Si3N4 nitride film is formed on a silicon substrate via a 5i02 film.
It relates to a method of processing memory elements, integrated circuits, etc. having an IDE-8 semiconductor structure.

In general, MIS (Metal-Insulator-
8emi conductor) ) transistor, for example MNOS.

MOS (Metal-Oxide-8micond
When manufacturing uctor) type transistors, the charge present in the gate insulating film is one of the factors that determines the threshold voltage VTR, so controlling the charge in the gate insulating film is important in manufacturing MIS) transistors and other devices. This kind of M
This is an important point in manufacturing a semiconductor device having an IS structure.

In insulated gate field effect transistors with MIS structures such as MOS and MNOS types, positive charges (+Q88) generally exist in the gate insulating film, and in P-channel MOS transistors, there is an enhancement type MOS transistor, and in N-channel MOS transistors, there is a positive charge (+Q88). It depends on the surface concentration of the substrate, but when the surface concentration is less than about 1×10166rrL, it becomes a depression type, and it becomes 1×10166rrL or less.
When it exceeds 16 crr1, it becomes an enhancement type.

Generally, in MOS and MNOS types, it is desirable to reduce +Q88 to reduce VTH, but in MOS type elements, when aluminum M is used for the gate electrode, the M evaporation After annealing at a heating temperature of about 400℃, M and H2O
H 2 generated by the + reaction penetrates into the SiO□ film and has the effect of reducing +Q88, and by undergoing such an annealing treatment, the VTR can be lowered.

However, in the case of a MNOS type structure having a nitride film, for example, the nitride film Si3N4 has the effect of blocking H+, and the above-mentioned annealing treatment, that is, annealing treatment at about 400°C, cannot reduce the +QS8. We cannot expect a decrease in □.

In the present invention, as a result of various experimental studies on semiconductor devices having such a nitride film, the +Q8S
We have now discovered a treatment method that can reduce VTH.

Hereinafter, the case where the present invention is applied to a field effect transistor or memory element having an MNO8 structure will be explained in detail.

In this case, first, as shown in FIG. 1A, an N-type semiconductor silicon substrate 1 having a resistivity of 2 to 3 Ω is prepared, and an insulating film, such as SiO
An insulating film 2 of about 500A is deposited by a well-known technique such as thermal oxidation treatment or chemical vapor deposition.
Source and drain diffusion windows 2s and 2d are opened in this by photoetching.

Next, as shown in FIG. 1B, the windows 2s and 2 of the insulating film 2 are
A source region 3s and a drain region 3d are formed by diffusing an impurity of a conductivity type different from that of the substrate 1, for example, P type, through d at a high concentration.

Next, as shown in FIG.
The oxide film formed during the diffusion of these regions on s and 3d is removed by etching.

As shown in the first diagram, a first gate insulating film, e.g., an SiO2 film, is formed on the region 3s and 3d from which the insulating film has been removed to a thickness of several 1 OA, e.g., 28X, by a well-known technique such as thermal oxidation. to adhere to.

Next, as shown in FIG. 1E, at least the first insulating film 4
A nitride film, such as a Si3N4 film 5, is formed overlying it to a thickness of 95 OA by a well-known technique, such as chemical vapor deposition.

In this way, the Si02 layer 4 and the Si3 layer are formed on the silicon substrate 1.
After forming the N4 layer 5, it is subjected to special annealing using the treatment method of the present invention.

That is, in the present invention, heat treatment is performed at 900 to 950°C in an atmosphere containing hydrogen of 50 φ or more, that is, in an atmosphere mainly composed of hydrogen, for 5 minutes or more, for example, 5 to 20 minutes, as desired.
Alternatively, heat treatment is performed for 10 minutes or more, for example, 15 minutes.

In this case, the atmosphere is selected such that, for example, the ratio H2/N2 of inert gas N2 and hydrogen H2 is 0.5 or more.

After this annealing treatment, as shown in FIG. 1F,
Electrode windows are opened on the circumferential regions 3s and 3d, and the source electrode 6 and drain electrode 7 are deposited in an open manner on these regions 3s and 3d, respectively. By depositing the gate electrode 8 on the gate insulating film having the N4 structure, the intended semiconductor device 9 having the MNO8 structure can be obtained.

In the above-mentioned treatment method of the present invention, the annealing treatment is performed by heat treatment at 900 to 950°C in an atmosphere mainly composed of hydrogen. The curve was measured as shown in FIG.

Curves 10 and 11 in the same figure were measured for comparison with the present invention; curve 10 is the C-■ curve without annealing treatment, and curve 11 is the C-■ curve at 860°C in a hydrogen atmosphere. C- when subjected to heat treatment for 15 minutes in
■It is a curve.

As is clear from comparing both lines 10 and 11, the threshold voltage ■T
It can be seen that the value of H (the part where C rapidly decreases) hardly changes.

Curve 12 is a treatment method according to the present invention, at 920°C,
C-V curve when annealing for 15 minutes,
In this case, it can be seen that the VTR is sufficiently lowered compared to curve 10.

Furthermore, curve 13 is the case where the same annealing treatment according to the present invention was performed at 950°C, and the C-■ curve hardly changes.

Incidentally, it has been confirmed that the C-■ curve of the products subjected to the same treatment at 1000°C and 1050°C almost coincides with curve 13, and furthermore, the same curve at 1100°C When annealing was performed, it was found that the curve almost coincided with curve 12.

As a result of conducting more detailed experiments, it was found that the change in the C-V curve was observed when the annealing temperature was selected to be 900°C or higher, and that the effect of lowering the VTR did not improve even when the annealing temperature exceeded 950°C. I found out that it will come.

In addition, FIG. 3 shows the measurement of the write amount of the memory transistor having the above-mentioned MNO8 structure. In this case, a pulse with a width of 100 m5ec was applied to the gate electrode to set the voltage .

Give and■. The writing amount when the value of is sequentially changed is measured as the flat band voltage ΔvFB (the flat band voltage before the memory is O).

In the figure, curves 14 and 14' are 9
This is a measurement curve obtained when annealing is performed at 20°C for 15 minutes.Even if the same treatment is performed at 950°C or 1000°C, there is almost no difference from this curve 14°14'. I couldn't.

In addition, in the figure, curve 15 is a measurement curve of the writing amount when processing is performed at 1100°C, and curve 16 is a measurement curve of the writing amount when no annealing processing is performed at all.As is clear from looking at these curves 15 and 16, It can be seen that the amount of writing decreases when the processing temperature becomes too high even when no annealing treatment is performed, and even when annealing treatment is performed.

Figure 4 shows the measurement curve of the retention capacity when electrons are stored in memory.In this case, measurements were taken at 300°C with no voltage applied. show.

Curve 17 in the figure shows the annealing treatment according to the present invention at 950°C.
C for 15 minutes, curve 18 shows the case where no annealing treatment is performed, and curves 19 and 20 show the case where annealing treatment is performed at 860° C. and 1100° C., respectively.

Looking at these curves, it is clear that as the annealing heating temperature increases, the retention ability decreases.

Figure 5 shows the BT treatment (B i
The change due to a s-Temperature process is measured, and the horizontal axis represents the processing time of this BT process.

Curve 21 in the figure shows the annealing treatment according to the present invention at 950°C.
When the CI is performed for 5 minutes, curve 22 is the case where no annealing treatment is performed, and curve 23 is the case where the annealing treatment is performed at 860°C.

In the annealing treatment at 1100°C, the changes caused by the BT treatment were extremely severe.

Regarding erasing and writing of positive charges, almost no change was observed between cases where the annealing process according to the present invention was performed and cases where the annealing process was not performed.

As is clear from the above explanation, 9000C to 950
It can be seen that the treatment method of the present invention, which involves annealing treatment in a hydrogen atmosphere at .degree.

In other words, the reason for selecting the above temperature range in accordance with the present invention is that below 900°C, the effect of reducing VT□ cannot be obtained much, and when it exceeds 950°C, various characteristics of the memory deteriorate. It's about coming.

However, in the present invention, annealing is performed in an atmosphere containing hydrogen, but for example, annealing is performed in an atmosphere containing only oxygen or an inert gas, or in a vapor such as a so-called forming gas containing a small amount of hydrogen. If treated, 9
In heat treatment at about 00 DEG C., there was almost no decrease in +QSS, and at temperatures higher than that, hysteresis appeared in the C-■ curve, resulting in very large instability for BT treatment.

Incidentally, when using the method of the present invention, no hysteresis appears in the C-■ curve.

Further, in the above example, the present invention is applied to a memory transistor having an MNO8 structure, but it can also be applied to various types of memory elements having nitride films or integrated circuits having drive elements. In addition, it has been confirmed that the present invention can be applied to an element having a SiO2 film formed by chemical vapor deposition or the like over a nitride film to produce similar effects.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing an example of a method for manufacturing a semiconductor device to which the processing method of the present invention is applied, and FIGS. 2 to 5 are characteristic curves for explaining the processing method of the present invention, respectively. 1 is a semiconductor substrate, 2 is an insulating film, 3s and 3d are source and drain regions, 4 is a SiO2 film, 5 is Si 3
The N4 film 8 is a gate insulating film.

Claims (1)

[Claims] 1. A method for processing a semiconductor device having a nitride film, which comprises annealing a semiconductor substrate having a nitride film at 900 to 950° C. in an atmosphere mainly containing hydrogen to lower the threshold voltage.