JPS5857782B2 - Syndrome generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a syndrome generation circuit for an information processing device using an error correction code.

It has long been well known that error correction codes are effective as a method to meet the increasing demands for high reliability for information processing equipment, and for meeting the demands for high reliability for these equipment. It is being

In conventional devices, syndromes are generated from a given binary information code and its error correction code by using a configuration in which a large number of logic integrated circuits are interconnected.

On the other hand, with the rapid development of integrated circuit technology in recent years, logic circuits used for syndrome generation can now be constructed by interconnecting one or several large-scale integrated circuits; When applied to one or several large-scale integrated circuits, conventional logic configurations are usually configured to reduce the amount of hardware, so they lack a general-purpose ratio that can meet various requirements, and the number of input/output terminals increases. There is.

An object of the present invention is to provide an integrated syndrome generation circuit for generating syndromes from information codes and error correction codes of different widths.

Another object of the present invention is to reduce the number of input terminals by allowing an error correction code input and a code input from another logic block for syndrome generation to be input to a common input terminal. The object of the present invention is to provide a programmable time generating circuit.

The circuit of the present invention includes: an information input terminal that provides an information code; a first code input terminal that provides a first error correction code; an information code from the information terminal; and an information code from the first error correction code input terminal. a calculation means for performing an exclusive OR operation based on the first error correction code of the calculation means; an output terminal for outputting the operation result from the calculation means; and an exclusive OR operation result given from the outside and the second error. a second code input terminal for inputting either one of a correction code and a correction code, and when the number of bits of the information code is equal to or smaller than the number of information input terminals, a second error correction code is provided to the calculation means; When the error correction code is larger, the remaining bits of the information code and the second error correction code are applied to the calculation means together with the exclusive OR result given from the outside to generate a syndrome.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention.

The circuit of the present invention has an input terminal 4 with a symbol P.

and Pl are inputted and given to the switching signal 6 to generate the code P.

and Pl to the signal line 9 or 10, and the switching circuit 1 and the information code d.

, dl, d2 and d3 from input terminal 3, error correction codes C6 and C1 from input terminal 5, and code P.

and Pl are input from signal line 9 or 10, and syndrome S is input from output terminal 7.

The basic circuit 11 includes a syndrome generating circuit 2 which outputs syndromes S2 and S3 from an output terminal 8.The relationship between these input and output codes is expressed by the following equations (1-1) to (1-4). (2-1) ~ (2-
4).

That is, when the switching signal is in the first state, Table 1 is information code.

, Dl, D2 and D3 error correction codes C6, C, , C2
and C3 and syndrome S.

, S, , 1-bit error correction is possible with the parity generation matrix showing the relationship between S2 and S3.

Note that information code D10-D'3+error correction code C'.

There is complete cyclicity between C10 and the information codes D'4 to D'7 and the C% peak and C'.

An embodiment in which the circuit of FIG. 1 is used independently in a single configuration will be described below.

Information codes (Do, Dl, D2 and D3) are input terminal 3
Also, error correction codes C2 and C3 are connected to input terminals 4. An exclusive OR is performed via the switching circuit 1 and the signal line 10, and the exclusive OR result is subjected to an exclusive OR operation with the error correction codes C6 and C1 given via the input terminal 5. , syndrome signal S from output terminal 7.

and Sl are output, and the syndrome S
2 and S3 are output.

This calculation is shown in equations (3-1) to (3-4),
Syndrome S of the parity generation matrix in Table 1.

, Sl, S2 and S3.

Next, referring to Table 2, the information code D10 to D
'7, error correction codes C'0 to C/, and a parity generation matrix showing the relationship between syndrome S'O-8'3, it is possible to correct a 1-bit error as in Table 1.

Further, referring to FIG. 2, the circuit shown in FIG. 2 uses two circuits in which a switching signal is applied to the switching terminal 6 so that the switching terminal 6 enters the second state.

Information code D'6 shown in Table 2. D1. D'2 and fj
3 through input terminal 3', error correction codes C'O and C
The signal is applied to the syndrome generating circuit 2' via 10, where an exclusive OR operation is performed, and the result of the operation is applied to the input terminal 4' via a connection line 12.

This and monitor information code/l, D'5. D'6 Oyohi v
The error correction codes C'2 and C10 are input to the syndrome generating circuit 2 through the input terminal 5 through the input terminal 3'.
given to.

As a result, the syndrome is output to the output terminal 7.

Note that the information codes D'O, D'1°false and D'3 and the information codes D'l, D'5. D5 and D'7 are applied to input terminals 3' and 3//, and similarly error correction codes C'o and C10 and error correction codes C'2 and C
10 was given, but this relationship may be reversed.

The exclusive OR result in this case is propagated via the connection line 13.

This relationship is expressed by the following formula.

As shown above, the basic circuit 11 shown in FIG.
and the second state, respectively, the information code.

-D3 and error correction codes C6 to C3.

The syndrome generation circuit described in detail of the present invention is sufficiently extensible, and the syndrome generation circuit that shares the input terminals of the syndrome generation code and the error correction code can be used in accordance with the information width used. If one or several syndrome generation circuits are used and multiple syndrome generation circuits are used, the mutual circuits should be interconnected, and the method of using the syndrome generation code and error correction code should be explained. The desired syndrome code can be generated by switching.

The present invention can use one or several single logic circuits for generating syndrome codes from information codes of different widths and their error correction codes, and generates error correction codes and syndromes input for each logic block. By making common use codes and changing the usage of these input terminals according to the information width, there is an effect that the number of input terminals can be reduced and circuits suitable for integrated circuits can be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit showing a first embodiment of the invention, and FIG. 2 is a diagram showing a second embodiment of the invention. From Figure 1 to Figure 2, % 1 t 1'+ 1//
...Switching circuit, 2, 2', 2//...
・・Syndrome generation circuit, 3.3', 3//・・・・
・・Input terminal・4・4′・4“°°゛・・・Input terminal,
5, 5', 5// ...input terminal, 6.6
'. 6tt , , , switching signal b 7 + 7' j
7〃...Output terminal, 8.8', 8//...
...output terminal, 9.9', 9//...signal line, 10.10', 10//...signal line, 12
゜13... Signal line.

Claims (1)

[Claims] 1. An information input terminal for manually inputting an information code, a first code input terminal for providing a first error correction code, and an exclusive input terminal based on the information code and the first error correction code. A calculation means for performing an OR operation, an output terminal for outputting the operation result from the operation means, and a second terminal for inputting either the exclusive OR operation result given from the outside or a second error correction code. a code input terminal; when the number of bits of the information code is equal to or smaller than the number of information input terminals, the second error correction code is applied to the calculation means; When it is thick, the remaining bits of the information code and the second
2. A syndrome generating circuit, characterized in that the syndrome is generated by applying an error correction code to the calculating means.