JPS5857913B2 - Manufacturing method of field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor.

Field effect transistors have high input impedance and are attracting attention as semiconductor devices compatible with electron tubes.

Static induction transistors also have these characteristics.

A further desired characteristic of the above-mentioned transistor is better high frequency characteristics, and various studies have been made.

A basic conventional field effect transistor will be described below.

FIG. 1 is a partial cross-sectional view of a conventional static induction transistor.

In the figure, 1 is a drain region made of an N-type image resistivity semiconductor layer, 2 is an N-type high resistivity semiconductor layer provided on the drain region 1, and 3 is formed by diffusion in the N-type high resistivity semiconductor layer 2. 4 is a gate region of a P-type semiconductor also formed by diffusion, 5 is a drain electrode, 6 is a source electrode, 7 is a gate electrode, and 8 is an N-type high resistivity semiconductor layer 2. , source region 3 and gate region 4
This is an insulating film that protects each surface and junction of the

The above-mentioned field effect transistor is manufactured by a process similar to that in the case of semiconductor 81.

First, an N-type high resistivity semiconductor layer 2 (with an impurity concentration of about 1015 cIrL-3 or more) is placed on an N-type image resistivity semiconductor layer (with an impurity concentration of about 1015 cIrL-3 or more) which will become the drain region 1.
(below) to eviximal growth.

Next, a 5I02 insulating film 8 is formed on this N-type high resistivity semiconductor layer 2 by thermal oxidation or the like.

This insulating film 8 is perforated into a predetermined shape by photoetching,
N-type and P-type impurities are selectively diffused here to form a source region 3 and a gate region 4.

Thereafter, the oxide film produced during selective diffusion is removed to form contact holes for forming electrodes.

Next, an electrode metal layer is formed by vapor deposition over the entire surface of the source region 3, gate region 4, insulating film 8, and drain region 1 other than those portions.

The electrode metal layer on the side of the source region 3 and gate region 4 is photoetched to form a source electrode 6 and a gate electrode 7, respectively, thereby completing the field effect transistor shown in FIG. 1.

The problems with this conventional field effect transistor will be explained in detail below.

FIG. 2 shows the distribution of electric lines of force in this field effect transistor when the source and drain potentials are kept constant and a lower potential is applied to the gate.

In the N-type high resistivity semiconductor layer 2, lines of electric force are generated from the drain region 1 and the source region 3 toward the gate region 4 due to the gate potential, as shown by arrows.

Among these, those that may be related to the drain current are electric fluxes 11 and 12 located within a region approximately the width of the source region 3 along the path vertically from the source region 3 to the drain region 1.
This is shown in .

The electric fluxes 9 and 10 are components that are not directly involved in controlling the drain current; the former controls the parasitic capacitance between the gate region 4 and the drain region 1, and the latter controls the parasitic capacitance between the source region 3 and the gate region 4.
This is the source of parasitic capacitance between the two.

The smaller these parasitic capacitances are, the better the high-frequency characteristics of this field effect transistor are, and the larger the proportion of the effective components shown by electric fluxes 11 and 12 of the total electric lines of force is, the better the mutual conductance (drain current/gate potential) of the transistor is. becomes larger.

In conventional field-effect transistors, the source and gate are on the same plane, and the space between them is filled with a semiconductor with a high dielectric constant, which increases the parasitic capacitance between the source and gate, which inhibits high-frequency characteristics. .

In addition, in the manufacturing process of a conventional field effect transistor, alignment of the gate region 4 with respect to the source region 3, alignment when forming contact holes for the source region 3 and gate region 4, and alignment of the source electrode 6 and gate electrode to the contact hole are performed. 7. Alignment is required during formation.

Since this positioning has limits due to mask alignment accuracy and photoetching processing accuracy, a dimensional margin must be provided each time positioning is performed.

In the conventional manufacturing method, alignment is required three times as described above, and it is difficult to reduce the widths and intervals of the source region 3, gate region 4, source electrode 6, and gate electrode 7. Ta.

The fact that the width of the gate region 4 cannot be reduced means that the parasitic capacitance between the gate and drain cannot be reduced.

For the reasons stated above, it has not been possible to improve the high frequency characteristics and mutual conductance of conventional field effect transistors.

In view of the fact that the drawbacks of the conventional field effect transistors are due to limitations in manufacturing technology, the present invention aims to alleviate the limitations in manufacturing technology and provide a field effect transistor with excellent high frequency characteristics and mutual conductance. The purpose is to obtain transistors.

An embodiment of the present invention will be described below.

FIG. 3 shows a cross-sectional view of a semiconductor substrate at one point in the manufacturing process to explain the manufacturing process of a field effect transistor using Si according to the present invention.

As shown in the figure, an N
An N-type source region 3 and a P-type gate region 4 are selectively diffused into a high-resistivity semiconductor layer 2 (impurity concentration of approximately 10@15 cm@-3 or less) as in the case of a conventional field effect transistor.

The diffusion depth is the same in the source region 3 and the gate region 4, or the gate region 4 is deep.

At this time, as shown in the figure, even if the source region 3 and gate region 4 are separated as shown in 20 or overlapped as shown in 21, in this invention, the part 20.21 is removed by etching as described later. So there is no problem.

That is, in the present invention, the alignment between the source region 3 and the gate region 4 may be slightly rough.

At this time, A7 or A7 is formed on the semiconductor surface on both the source/gate side and the drain side to become the source electrode, gate electrode, and drain electrode, and to serve as a mask during etching.
Deposit a metal layer containing u.

Next, as shown in FIG. 4, the source electrode 6 on the source region 3 is
, a gate electrode 7 and a drain electrode 5 on the gate region 4
The unnecessary metal layer is removed by photo-etching, leaving behind.

Next, in order to improve the compatibility between these electrode metals and the semiconductor, sintering is performed at about 300 to 450°C.

Next, using the source electrode 6 and gate electrode 7 as masks, S
i Semiconductor in nitric acid, hydrofluoric acid, acetic acid (volume ratio 6:l:2
) Etching by mixed group.

According to this etching solution, the etching rate of Si can be reduced to 1
Then, for Al, it is l/10. Since Au is almost zero, these metals have a sufficient masking effect.

Since the etching progresses not only in the depth direction but also in the lateral direction, a state in which the semiconductor region directly below each electrode remains and is automatically aligned as shown in FIG. 4 is obtained.

The etching depth in the depth direction is equal to or greater than the diffusion depth of the source region 3.

Finally, low temperature CVD method (Chemical VaporD)
A glass insulating film 8 is used to cover the semiconductor on the source/gate side and each electrode to protect the surface.

According to the manufacturing method of the present invention, the width of the source region 3 and gate region 4 can be made smaller than the width of the source electrode 6 and gate electrode 7, and the width of the electrode is 1 μm or less because dimensional tolerance is not required for alignment. (-Since the width of the gate region 4 can be made extremely small, the parasitic capacitance between the gate and drain becomes small.

It is also a simple manufacturing method that requires fewer alignments and requires less precision.

FIG. 5 shows the distribution of electric lines of force in a field effect transistor manufactured according to the present invention in comparison with FIG. 2, which describes a conventional field effect transistor.

Since the space between the source region 3 and the gate region 4 is filled with a glassy substance with a low dielectric constant, the lines of electric force between this region are extremely small compared to conventional ones, and the lines of electric force are many in the semiconductor. The proportion of the electric flux 11 that is effective for control increases.

In other words, the mutual conductance becomes large.

FIG. 6 shows a field effect transistor manufactured according to another embodiment of the present invention, in which the diffusion depth of the gate region 4 is made deeper than the diffusion depth of the source region.

By doing so, an electric field due to a reverse voltage applied between the source and the gate is not applied to the corner portion of the mesa bottom surface of the gate region, resulting in an advantage that the withstand voltage between the source and the gate is increased.

Although the above description has been made regarding a device based on an N-type semiconductor, it goes without saying that a device based on a P-type semiconductor may also be used.

Furthermore, although the electrostatic induction type transistor has been described as an example, it goes without saying that the present invention can also be applied to field effect type transistors and provide excellent high frequency characteristics.

As detailed above, according to the present invention, it is possible to reduce the width of the gate region and the source region and reduce the flux of electric lines of force between them, thereby reducing parasitic capacitance and obtaining good high frequency characteristics. At the same time, excellent mutual conductance can be achieved.

In addition, despite the simple method, which requires rougher alignment and fewer alignments than conventional methods, selective etching using a metal electrode as a mask can produce field-effect transistors with the above performance (deprecated). It is something that can be done.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional structural diagram of a conventional static induction transistor.
FIG. 2 is a diagram showing the distribution of electric lines of force inside the transistor shown in FIG. 1, FIG. 3 is a cross-sectional structural diagram of a semiconductor substrate at one point in the manufacturing process of the transistor of the present invention, and FIG. 4 is a diagram of the present invention. A cross-sectional structural diagram showing a static induction type transistor manufactured according to one embodiment, FIG. 5 is a diagram showing the distribution of electric lines of force inside the transistor shown in FIG. 4, and FIG. 6 is a diagram showing another embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram showing a static induction transistor manufactured by. In the figure, 1 is a drain region, 2 is a high resistivity semiconductor layer,
3 is a source region, 4 is a gate region, 6 is a metal layer on the source region, 7 is a metal layer on the gate region, and 8 is an insulating film.

Claims (1)

[Claims] 1. selectively diffusing a source region having the same conductivity type as the semiconductor layer and a gate region having the opposite conductivity type to the source region on one main surface of a semiconductor layer having a predetermined conductivity type; a step of forming a drain region having the same conductivity type as the semiconductor layer on the other main surface of the semiconductor layer; a step of forming a metal layer in a predetermined pattern on each of the gate region and the source region; A method for manufacturing a field effect transistor, comprising the step of selectively etching the semiconductor layer from the source regions f and gate region side to at least the diffusion depth of the source regions using the metal layer of the predetermined pattern as a mask. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the diffusion depth of the gate region is set to be the same as or deeper than the diffusion depth of the source region. 3. The method for manufacturing a field effect transistor according to claim 1, wherein the metal layer having a predetermined shape is a metal layer comprising an AA deposited layer or an Au deposited layer.