JPS6047610B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing device, particularly a random access type branch table buffer that collectively stores branch instructions, and a group of sequential processing instructions that are sequentially executed in a predetermined order. The present invention relates to a data processing device which includes a random access sequential instruction control memory for collectively storing data, and is capable of changing the processing mode at any time by exchanging the contents of the branch table buffer.

For example, in a compiler, there is a program called a transition matrix, but when attempting to configure hardware that can execute such processing, there are many difficulties in using the conventionally known microprogram format. This is due to the fact that sequential processing instructions that are executed sequentially in a predetermined order and branch instructions that branch according to conditions coexist. The present invention aims to solve the above-mentioned problems, and is a data processing device that has a memory that separately stores the two types of instructions mentioned above, and that allows the processing mode of the data processing device to be changed at any time. is intended to provide.

Therefore, the data processing device of the present invention is a microprogram-based data processing device having a control memory in which a microprogram is stored, and a random access type branch table for collectively storing branch instructions in the microprogram. a buffer, a random access sequential instruction control memory that collectively stores a group of sequential processing instructions to be executed in a predetermined order, a mode for accessing the branch table buffer by instructions, and It has a mode register in which a mode for accessing the sequential instruction control memory is set, and a logical processor address register in which address information for accessing the branch table ◆ buffer is set,
Based on the contents of the mode register, the logical processor in the branch table buffer is configured to access the address specified by the contents of the address register, and in the order described above based on the contents of the branch table buffer. The specified start address in the instruction control memory is accessed to execute subsequent processing, and at the point when the substantially end of the subsequent processing has been executed, the branch table buffer is accessed and the sequential instruction control memory is accessed. It is characterized in that it is configured to move on to execution of other subsequent processing. This will be explained below with reference to the drawings. The figure shows the configuration of an embodiment of the present invention.

In the figure, 1-0 is random●Access type branching table●
A buffer that stores instructions all at once.
1-1 is a sequential instruction control memory in which a group of instructions 4 to be executed sequentially in a predetermined order is stored; 2 is a storage data register; and 3 is a decoder which is a data register. 2 is a storage data address register which decodes the microinstruction loaded into the register and executes the process. Access to bull buffer 1-0 and sequential instruction control memory 1-1 ◆The address is set, and 5 is a branch condition control unit, which is one of multiple branch destinations read according to a branch instruction. is selected according to the machine state, 6 is local storage, 7 is a logical processor address ◆ register in which the access address for the above branch table buffers 1-0 is set, 8 9 is a mode register in which mode instruction information indicating whether to access buffer 1-0 or sequential instruction control memory 1-1 is set in the branch table mentioned above; 9 is a link
The address buffer register is one in which the contents of the logical processor address register 7 are transferred and held, 10 and 11 are latches, and 12 and 13 are AND circuits. In the case of the present invention, only the branch instructions A, B, etc. shown in the diagram are stored together in the branch table buffer 1-0, and once the start address is specified, the following processes are executed in a predetermined order. Only the following sequential instruction groups Pl, P2, etc. are collectively stored in the sequential instruction control memory 1.
-1.

As is well known, the microinstruction, which is one of the sequential instructions read out from the memory 1-1, has a next address designation part NA, and as will be described later, the microinstruction is read out from the memory 1-1 one after another according to the contents of the next address designation part NA. The microinstructions to be executed are read out. Needless to say, the microinstructions read from the branch table buffer 1-0 and the sequential instruction control memory 1-1 are stored in the storage
Loaded into data register 2 and decoded by decoder 3. Based on the decoded output, bus gates and the like are controlled to be turned on or off in order to execute the operation specified by the microinstruction, as is known in the art. The contents of the logical processor address register 7 can be set to an arbitrary value by a command, or can be set at any time by a counter or the like.

Note that the set value corresponds to the storage address of the illustrated branch instruction A and the branch instruction illustrated B. Therefore, by setting the value appropriately, the ordered instruction group P1
, P2, etc. and their order can be easily changed. Further, the contents of the mode register 8 can be arbitrarily rewritten by an instruction read from the sequential instruction control memory 1-1. Now, with a value set in logical processor address register 7 and its contents transferred to link address buffer register 9, the contents of mode register 8 are set to logical RO.
Suppose that it is switched to J.

As a result, AND circuit 12 is turned off and AND circuit 13 is turned on. The contents of the link address buffer register 9 are then loaded into the storage address register 4 and temporarily held in the latch 11. At this time, the above mode ● Contents of register 8 RO. J is added to the first bit of the contents of the storage address ◆register 4. As a result, since the first bit is 10, the predetermined address of the branch table buffer register 1-0 is accessed and loaded into the data register 2. That is, the branch instruction stored at the address, for example A, is read out, decoded and executed by the decoder 3, and the microcontroller stored at the first address of a group of sequential instructions that will be the branch destination, for example. Instructions are read from sequential instruction control memory 1-1. The contents of the mode register 8 are then returned to 1. At this time, the branch condition control unit 5 determines the branch destination based on the machine state, and one of the plurality of instructions read out, for example, the first instruction of the instruction group P1, is selected and loaded into the data register 2. . Since the contents of the mode register 8 have become RlJ as described above, the AND circuit 12 is turned on in the subsequent processing, and the contents of the next address part NA in the microinstruction loaded into the data register 2 are changed to the storage When set in the address register 4 and latched in the latch 11, the contents of the mode register 1 are added to the first bit, and thereafter the instructions of the instruction group P1 are sequentially read out and executed.

During this time, the contents of the logical processor address register 7 are updated and the contents of the link address buffer register 9 are updated.
held within. Then, the contents of the mode register 8 are switched to RO by, for example, the last instruction of the instruction group P1. As a result, the predetermined location of the branch table buffer 1-0 is accessed again, and, for example, the illustrated branch instruction B is read out. Thereafter, processes are executed one after another in the same manner, but while the instructions from the sequential instruction control memory 1-1 are being executed sequentially, it can be determined which branch instruction should be prepared next depending on the process.

Using this point, link address ● buffer ● Based on the contents of register 9, branch table buffer 1
Branch instructions can be prefetched from -0. In this case, it is preferable to make the access addresses for the branch table buffer 1-0 and the sequential instruction control memory 1-1 independent. Branch table ●Buffer 1
The contents of -0 can be replaced, for example, with the contents of a console file (not shown), if desired. Furthermore, it can be rewritten by a macro instruction written to the main memory as necessary. Furthermore, it will be appreciated that the contents of the sequential command control memo I-1 can also be exchanged with the contents of the console file, if desired. As explained above, according to the present invention, the branch table ●Buffer 1-
Since the branch instructions are stored together in 0,
By exchanging the contents of the branch table buffer 1-0, it becomes possible to take any processing mode. The contents of the logical processor address register 7 can then be selected by a conventionally known microprogram method.
The degree of freedom is further increased compared to conventional data processing devices, and it is also possible to directly change detailed steps of a program.

[Brief explanation of the drawing]

The figure shows the configuration of an embodiment of the present invention.

Claims (1)

[Claims] 1. A microprogram type data processing device having a control memory in which a microprogram is stored,
A random access type branch table buffer that collectively stores the branch instructions in the above microprogram, and a random access type order buffer that collectively stores a group of sequential processing instructions that are executed in a sequentially determined order. an instruction control memory; a mode register in which a mode for accessing the branch table buffer and a mode for accessing the sequential instruction control memory are set by the instruction;
A logical processor address register in which address information for accessing the branch table buffer is set, and based on the contents of the mode register, the logical processor address register in the branch table buffer is set. It is configured to access the address specified by the leaf, and based on the contents of the branch table buffer, accesses the specified start address in the sequential instruction control memory and executes the subsequent processing, and also executes the subsequent processing. A data processing device characterized in that the branching table buffer is accessed at the time when substantially the end of the processing is executed, and the execution of other subsequent processing in the sequential instruction control memory is started. 2. The data processing device according to claim 1, wherein the data processing device is configured to switch the contents of the mode register by a microinstruction stored in the sequential instruction control memory. 3. Claim 1 or 2, characterized in that the content of the branch table buffer is configured to be rewritten by a microinstruction.
The data processing device described in Section 1.