JPS588080B2 - Error check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error checking method in a storage device in an electronic computing organization, and more particularly to a method for checking competing signal systems within the storage device.

In a storage device, when a storage element is used to read or write stored information or refresh stored information, several types of timing are generally required for the storage element, while a common timing is required for each operation of the storage element. There is.

Conventionally, checks in such cases include checking whether the read request, write request, refresh request selection or priority determination circuit operates correctly, checking between each other's signals, or checking between each timing of the storage element. When each circuit or only one circuit is checked, if there are many signals to be checked, the circuit becomes complicated, and malfunctions caused in the previous circuit cannot be checked in the subsequent circuit.

As described above, when a storage element in a storage device is caused to read or write stored information or refresh stored information, several types of timing are generally required for the storage element. In each operation, there is a common timing.

These timings are determined by first using one basic signal that operates the storage element from one request selected from among the operation requests, and then generating several types of timing required for the storage element from that signal to match each request. It's working.

In this process, when each operation request is selected, if the selection is not performed correctly, it will lead to malfunction of the memory element.
This leads to destruction of memory information or errors in memory information.

In order to eliminate such a problem, in the present invention, a signal having a predetermined time width of a predetermined time is used in one signal line that generates the timing necessary for the storage element from the selected signal. By checking that there is no signal other than the predetermined signal, it is possible to check the previous circuit for selection or priority determination, and to guarantee several types of timing that are later created from this signal.

In general, several types of timing are required for reading or writing stored information, or refreshing operations at fixed intervals necessary for retaining stored information, and storage elements that have common timing for each operation are used. When using a CPU and a storage device that generates a refresh request within the storage device,
When a request to read or write stored information from a CPU to a storage device and a refresh request are mutually independent, a conflict occurs within the storage device.

When one request is selected from these competing requests according to a predetermined priority order and the storage element is operated according to that request, the selection circuit operates correctly and the timing is set for the storage element according to one request signal. In the present invention, a check as to whether this occurs is performed as follows.

That is, after the selection circuit, it is checked whether the signal has a predetermined time width and a predetermined time width on one signal line that generates the timing of the storage element, and that there is no signal other than the predetermined signal. .

As a result, the circuit in the previous stage is checked and the circuit in the subsequent stage is guaranteed, so that the circuit becomes less complex than the conventional system in which a large number of signals are checked in each circuit.

Furthermore, according to the present invention, depending on the malfunction of the preceding stage circuit,
This eliminates cases where the circuit cannot be checked in the subsequent stage.

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a schematic diagram of a storage device.

In the figure, CPU is a central processing unit, M is a storage device, and R
EG is a register, PRI is a priority determination circuit, MEM is a semiconductor memory that requires refreshing, T is a circuit that generates a refresh request signal, and DET is an error detection device.

Requests for the semiconductor memory MEM are accepted by the register REG, and one of the accepted requests is selected by the priority determination circuit PRI.

A signal resulting from the selection is supplied to the semiconductor memory MEM, and this signal is checked by the error detection device DET.

When this priority determination circuit PRI does not operate correctly, that is,
A signal of a predetermined width is not given to the semiconductor memory MEM at a predetermined timing.

In such a case, various timing signals for operating the semiconductor memory are not generated correctly, and the semiconductor memory cannot be operated correctly.

In order to avoid such a situation, the present invention detects an error in the output signal of the priority determining circuit PRI.

Fig. 2 shows the error detection device of the present invention, and Fig. 3 shows the error detection device of the present invention.
It is a time chart of each part of the figure.

Referring to FIG. 2 showing the circuit configuration and FIG. 3 showing the time chart, the embodiment of the present invention has the following advantages: , check whether there is only one signal with a defined time width.

In the figure, 0 to 10 are clock signals, and when checking a signal of a predetermined width delayed by a predetermined time from the request signal 11 to the semiconductor memory, the request signal 11 is sent to the logic circuit 30,
31, 32, 33 and the delay line 50, the input signal of the delay line 51 is differentiated by the set input signal of the FF 54, which determines the time of the execution cycle 12, and the input signal of the delay line 51, which creates the time to check the 1 signals 13, 14 to be checked. make.

For the sake of explanation, the signal 13 is a signal that is checked to be a pulse of a predetermined width at a predetermined timing, and the signal 14 is an erroneous pulse that appears during the same execution cycle.

This delay line 51 produces strobe pulses 15, 16, 17, 18 and 19, 20 at the times to be checked.

Now, if the signal to be checked is 13, first pulse 1
5 is generated, and from the time determined by this, the signal 1
If 3 is fast, the logical product 35 of the pulse 15 is taken and becomes the set pulse of FF5Q as an error, and an error signal 21 is generated.

Next, if the signal 13 does not arrive at the time determined by the pulse 16, the logical product 37 with the pulse 16 is taken and an error is determined, which becomes a set pulse for the FF 61, and an error signal 22 is generated.

Furthermore, if the signal is not output until the time determined by pulse 17, the logical product of pulse 17 and 39 will be taken and an error will occur.
This becomes a set pulse of F62 and an error signal 23 is generated.

Finally, if the signal continues to be output after the time determined by the pulse 18, the logical product 40 with the pulse 18 is taken, resulting in an error, which becomes a set pulse for the FF 63, and an error signal 24 is generated.

On the other hand, the logical product 42 of the signal to be checked 13 and the execution cycle 12 is taken, and the resulting pulse is first used as a set pulse for the FF 65 and as a clock for the D type FF 55 at the next stage.

In addition, by using the output of FF55 as the data of the next stage D type FF66, when the logical product 42 of the signal to be checked 14 and the execution cycle 12 is obtained again during the same execution cycle 12, the output of FF55 and the data of the previous stage FF65 logical product 4
4 is removed, and an error signal 25 is generated.

A logical sum 45 of the above error signals 21, 22, 23, 24, and 25 is taken, and a logical product 46 is taken with timing 19 when an error should be made, to generate an error signal 26.

By the above method, it is possible to check whether the signal to be checked is occurring from a predetermined time to a predetermined time, and whether only one signal has occurred.

On the other hand, in these FFs 60 to 66, the logical product 48 with the reset signal 20 cannot be obtained due to the occurrence of an error, and the contents are retained.

It is reset by the reset 20 when there is no error, and by Re Set from the outside when an error occurs.

As explained above, the present invention selects one signal from among multiple signals that issue a request to a storage device in order of priority.
When creating a signal that spans the entire storage device using a signal, it is important to ensure the selection circuit, and by using a configuration that checks the time and duration that the selected signal should be generated, as well as the number of times it occurs, it is possible to This has the effect of conducting strict checks and guaranteeing subsequent circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a storage device, FIG. 2 is an embodiment of the present invention,
FIG. 3 shows a time chart of the signals in FIG. In the figure, MEM is a semiconductor memory, DET is an error detection device, T is a refresh request signal generation circuit, REG is a reception 1/register, CPU is a central processing unit, 13 is a signal to be checked, 14 is a signal other than the specified one, 51 is a delay line that generates timing signals 15 to 19 for checking.

Claims (1)

[Claims] 1 Select one of a refresh request signal generated internally and a read or write request signal from the central processing unit in a predetermined order, and operate the storage element based on the selected request signal. In a storage device that generates a timing signal for a memory operation to perform a memory operation, a first timing signal that is delayed by a certain period of time from the selected request signal, based on the selected request signal;
further delayed than the first timing signal and
a second timing signal that does not overlap with the timing signal; a third timing signal that is further delayed than the second timing signal; and a third timing signal that is further delayed than the third timing signal. means for generating a fourth timing signal that does not overlap; a first flip-flop that holds a logical condition signal for the memory operation timing signal and the first timing signal; a second flip-flop holding a logical condition signal for the second timing signal;
and a fourth flip-flop that holds a logic condition signal between the memory operation timing signal and the fourth timing signal. An error check method characterized in that it is checked based on the output of the memory operation timing signal whether or not the memory operation timing signal is generated at a regular time and has a regular time width.