JPS588098B2 - Relay Seigiyo Cairo - Google Patents
Relay Seigiyo CairoInfo
- Publication number
- JPS588098B2 JPS588098B2 JP49085467A JP8546774A JPS588098B2 JP S588098 B2 JPS588098 B2 JP S588098B2 JP 49085467 A JP49085467 A JP 49085467A JP 8546774 A JP8546774 A JP 8546774A JP S588098 B2 JPS588098 B2 JP S588098B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- relay
- state
- electronic timer
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Relay Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
本発明はリレー制御回路に関するもので、リレーの切換
状態を電子タイマー回路で保持することにより信頼性と
耐久性の向上を計ることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relay control circuit, and an object of the present invention is to improve reliability and durability by maintaining the switching state of a relay using an electronic timer circuit.
1は電源トランス、2は定電圧供給回路で整流用ダイオ
ード3と平滑用コンデンサ4、定電圧供給ラインを導通
、非導通に制御するトランジスタ5、ツエナーダイオー
ド6および抵抗7とより構成し、電圧Voを次降の回路
に供給する。1 is a power transformer, 2 is a constant voltage supply circuit, which is composed of a rectifier diode 3, a smoothing capacitor 4, a transistor 5 for controlling the constant voltage supply line to be conductive or nonconductive, a Zener diode 6, and a resistor 7; is supplied to the next downstream circuit.
8はリレー回路9の第一状態を保持すると共に第二状態
に切換える第一電子タイマー回路で該タイマー回路は抵
抗11とコンデンサ12よりなる充電回路、13と抵抗
14,15及び16よりなる電圧分割回路17と、アノ
ードAは前記充電回路13の中間点に接続し、ゲートG
は電圧分割回路17の抵抗15に半固定状態に接続し、
カソードKはトリガ用抵抗18を介して電源供給側に接
続した第一PNPN型制御整流素子(以下第一PUTと
いう)19とより構成している。8 is a first electronic timer circuit that maintains the first state of the relay circuit 9 and switches it to the second state; this timer circuit includes a charging circuit consisting of a resistor 11 and a capacitor 12; The circuit 17 and the anode A are connected to the intermediate point of the charging circuit 13, and the gate G
is semi-fixedly connected to the resistor 15 of the voltage divider circuit 17,
The cathode K is constituted by a first PNPN type controlled rectifier (hereinafter referred to as first PUT) 19 connected to the power supply side via a trigger resistor 18.
前記リレー回路9は切換接点b,aを有するリレー20
と該リレーの通電を制御するシリコン制御整流素子(以
下SCRという)21を直列接続して構成するもので前
記SCR21のゲートGは前記トリガ用抵抗18に接続
している。The relay circuit 9 includes a relay 20 having switching contacts b and a.
and a silicon controlled rectifier (hereinafter referred to as SCR) 21 that controls the energization of the relay are connected in series, and the gate G of the SCR 21 is connected to the trigger resistor 18.
21は前記リレー回路9の第二状態を保持すると共に後
述する復帰回路へ出力する第二電子タイマー回路で前記
第一電子タイマー回路8と同様抵抗22とコンデンサ2
3よりなる充電回路24と、抵抗25,26及び27よ
りなる電圧分割回路28と、アノードAは前記充電回路
24の中間点に接続し、ゲートGは電圧分割回路28の
抵抗26に半固定状態で接続し、カソードKはトリガ用
抵抗29を介して電源供給側に接続した第二PUT30
とより構成している。Reference numeral 21 denotes a second electronic timer circuit which maintains the second state of the relay circuit 9 and outputs the output to a recovery circuit which will be described later, which includes a resistor 22 and a capacitor 2, similar to the first electronic timer circuit 8.
3, a voltage dividing circuit 28 consisting of resistors 25, 26, and 27, the anode A is connected to the midpoint of the charging circuit 24, and the gate G is semi-fixed to the resistor 26 of the voltage dividing circuit 28. The cathode K is connected to the second PUT 30 connected to the power supply side via the trigger resistor 29.
It is composed of
而して31はトランジスタ5をOFF状態として前記リ
レー20に対する電圧の供給を遮断して第二状態から第
一状態に復帰せしめる復帰回路で該復帰回路はアノード
Aをトランジスタ5のベースに接続し、ゲートGを第二
PUT30のトリガー用抵抗20に接続し、カソードK
を電源供給側に接続したSCR32を有している。Reference numeral 31 denotes a return circuit that turns off the transistor 5, cuts off the voltage supply to the relay 20, and returns the second state to the first state; the return circuit connects the anode A to the base of the transistor 5; Connect the gate G to the trigger resistor 20 of the second PUT 30, and connect the cathode K
It has an SCR 32 connected to the power supply side.
次に動作について説明する。Next, the operation will be explained.
定電圧供給回路2より第一電子タイマー回路8に電圧が
印加されると充電回路13のコンデンサ12が抵抗11
を通して時定数T1=R1C1で充電され、第一PUT
19のアノード電圧■Aがゲート電圧■Gにほほ等しく
なると前記第一PUT19は導通してカソードに接続し
たりトリガー用抵抗18にパルス状の電圧を生起する。When voltage is applied to the first electronic timer circuit 8 from the constant voltage supply circuit 2, the capacitor 12 of the charging circuit 13 becomes the resistor 11.
charged with time constant T1=R1C1 through the first PUT
When the anode voltage (A) of the first PUT 19 becomes approximately equal to the gate voltage (G), the first PUT 19 becomes conductive and connects to the cathode, or generates a pulse voltage in the trigger resistor 18.
この電圧はSCR21のゲートに供給されてSCRが導
通すると共にリレー20も導通し、その接点Cは第一状
態を保持するb側より第二状態を保持するa側に切換わ
る。This voltage is supplied to the gate of the SCR 21, and the SCR becomes conductive, and the relay 20 also becomes conductive, and its contact C switches from the b side, which maintains the first state, to the a side, which maintains the second state.
前記リレー20の導通と同時に第二電子タイマー回路2
1の充電回路24も時定数T2−R2C2で充電され第
二PUT30のアノード電圧がゲート電圧にほぼ等しく
なると前記第二PUT30が導通してカソードに接続し
たトリガー用抵抗29にパルス状の電圧が生じる。At the same time as the relay 20 becomes conductive, the second electronic timer circuit 2
The charging circuit 24 of No. 1 is also charged with a time constant T2-R2C2, and when the anode voltage of the second PUT 30 becomes almost equal to the gate voltage, the second PUT 30 becomes conductive and a pulse-like voltage is generated in the trigger resistor 29 connected to the cathode. .
このパルス状の!圧が復帰回路31のSCR32のゲー
トに印加されて前記SCR32が導通し、トランジスタ
5のベース電圧は低下しトランジスタ5はOFFする。This pulsed! Voltage is applied to the gate of the SCR 32 of the recovery circuit 31, the SCR 32 becomes conductive, the base voltage of the transistor 5 decreases, and the transistor 5 is turned off.
従って、トランジスタ5のコレクタとエミツタ間は非導
通となり、第一、第二の電子タイマー回路821及びリ
レー回路9への定電圧供給ラインは非導通となる。Therefore, the collector and emitter of the transistor 5 become non-conductive, and the constant voltage supply line to the first and second electronic timer circuits 821 and the relay circuit 9 becomes non-conductive.
よって、第一電子タイマー回路8の第一PUT19は非
通電となると共にSCR21もまた非通電となる。Therefore, the first PUT 19 of the first electronic timer circuit 8 is de-energized, and the SCR 21 is also de-energized.
また、リレー回路9へノ定電圧供給は遮断されるためリ
レー20の両端に加わる電圧はゼロとなり、リレー20
の接点Cは第二状態を保持するa側より第一状態を保持
するb側に切換わる。Further, since the constant voltage supply to the relay circuit 9 is cut off, the voltage applied to both ends of the relay 20 becomes zero, and the relay 20
The contact point C switches from side a, which holds the second state, to side b, which holds the first state.
一方第二電子タイマー回路21の第二PUT30は非通
電となると共にSCR32もまた非導通となる。On the other hand, the second PUT 30 of the second electronic timer circuit 21 becomes non-conductive, and the SCR 32 also becomes non-conductive.
従って、定電圧供給回路2のトランジスタ5は再びON
し、第一、第二電子タイマー回路8,21及びリレー回
路9に定電圧は供給される。Therefore, the transistor 5 of the constant voltage supply circuit 2 is turned ON again.
However, a constant voltage is supplied to the first and second electronic timer circuits 8 and 21 and the relay circuit 9.
第2図はリレーのタイムチャードを示すもので第一状態
はT1−T1C1の間保持されまた第二状態はT2−R
2C2の間だけ保持される。Figure 2 shows the time chart of the relay, where the first state is held between T1-T1C1 and the second state is T2-R.
It is held only for 2C2.
本発明によるリレー制御回路は上述の如く、定電圧供給
ラインを導通、非導通に制御するトランジスタを含む定
電圧供給回路と、リレーの第一状態を保持すると共に第
二状態に切換える第一電子タイマー回路と、前記第二状
態を保持すると共に復帰回路へ出力する第二電子タイマ
ー回路と、該回路の終段出力により前記第二状態から第
一状態に復帰せしめる復帰回路とよりなるものであるか
らリレー切換及び保持動作が確実に行なわれる。As described above, the relay control circuit according to the present invention includes a constant voltage supply circuit including a transistor that controls the constant voltage supply line to be conductive or nonconductive, and a first electronic timer that maintains the first state of the relay and switches it to the second state. A second electronic timer circuit that maintains the second state and outputs the output to the return circuit, and a return circuit that returns the second state to the first state by the final stage output of the circuit. Relay switching and holding operations are performed reliably.
又、第一、第二の電子タイマー回路及び復帰回路に接点
の溶着等の故障の生じるところのリレー及びリレー接点
から構成されるリセット回路等を接続する必要はなく、
回路の簡素化が図れ、信頼性及び耐久性が向上し実用上
有益な効果を奏する。In addition, there is no need to connect a reset circuit, etc. consisting of a relay and relay contacts, which can cause failures such as welding of contacts, to the first and second electronic timer circuits and the reset circuit.
This simplifies the circuit, improves reliability and durability, and has practical effects.
第1図は本発明によるリレー制御回路の電気回路図、第
2図はリレーの切換動作を示すタイムチャート図である
。
2……定電圧供給回路、8……第一電子タイマー回路、
9……リレー回路、21……第二電子タイマー回路、3
1……復帰回路。FIG. 1 is an electric circuit diagram of a relay control circuit according to the present invention, and FIG. 2 is a time chart showing the switching operation of the relay. 2... Constant voltage supply circuit, 8... First electronic timer circuit,
9... Relay circuit, 21... Second electronic timer circuit, 3
1...Return circuit.
Claims (1)
ジスタを含む定電圧供給回路と、リレーの第一状態を保
持すると共に第二状態に切換える第一PUTを含む第一
電子タイマー回路と、前記リレーの第二吠態を保持する
と共に復帰回路に出力する第二PUTを含む第二電子タ
イマー回路と、前記出力により動作し前記トランジスタ
をOFFとすることにより前記第二状態から第一状態に
復帰せしめる復帰回路とより構成することを特徴とする
リレー制御回路。1. A constant voltage supply circuit including a transistor that controls the constant voltage supply line to be conductive or nonconductive, a first electronic timer circuit including a first PUT that maintains the first state of the relay and switches it to the second state, and the relay. a second electronic timer circuit including a second PUT that maintains the second bark state and outputs the output to the return circuit; and a second electronic timer circuit that is operated by the output and turns off the transistor to return the second state to the first state. A relay control circuit characterized by comprising a return circuit and a return circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49085467A JPS588098B2 (en) | 1974-07-24 | 1974-07-24 | Relay Seigiyo Cairo |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49085467A JPS588098B2 (en) | 1974-07-24 | 1974-07-24 | Relay Seigiyo Cairo |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5113564A JPS5113564A (en) | 1976-02-03 |
| JPS588098B2 true JPS588098B2 (en) | 1983-02-14 |
Family
ID=13859679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49085467A Expired JPS588098B2 (en) | 1974-07-24 | 1974-07-24 | Relay Seigiyo Cairo |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS588098B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334118Y2 (en) * | 1986-12-25 | 1988-09-09 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS472054U (en) * | 1971-01-28 | 1972-08-23 |
-
1974
- 1974-07-24 JP JP49085467A patent/JPS588098B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5113564A (en) | 1976-02-03 |
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