JPS589458B2 - Timer control method in data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer control system that allows multiple microprocessors to share one timer subroutine.

Bank terminal equipment uses many types of input/output devices, such as printers, bankbook inhalers, keyboards, plasma displays, and card leagues.

Multiple microprocessors are installed to control the input/output devices mentioned above, but in conventional technology, each microprocessor operates independently and no communication means is provided between each microprocessor. It wasn't.

Therefore, each microprocessor is equipped with the same program, and the entire system has a plurality of the same programs.

One such program is a timer subroutine.

The timer subroutine is a routine that sets a timer value in a predetermined area of memory in response to a request, decrements the timer value by 1 at regular time intervals, and notifies that the timer is up when the content of the area becomes zero. It is.

This timer is used, for example, as follows.

When setting a passbook in the passbook suction device, set the timer to start the operation, and when the time is up,
Detects whether or not the passbook is located in a predetermined position. If it is in a predetermined position, performs corresponding processing, such as printing processing, etc.; if it is not in a predetermined position, performs other corresponding processing. For example, it performs processing such as displaying an alarm.

Each microprocessor in the bank terminal device mentioned above always uses a plurality of timers for time monitoring.

The timer subroutine has a capacity of, for example, about 300 bytes, and if three microprocessors are used in a bank terminal, the conventional technology requires about 1K byte of memory for the timer subroutine. Requires capacity.

It is completely wasteful to prepare a plurality of identical timer subroutines in one device, and therefore it is desirable that one timer subroutine be shared by a plurality of microprocessors.

The present invention is based on the above considerations, and provides a timer subroutine sharing method that allows one timer subroutine to be shared by multiple microprocessors in a system where multiple microprocessors exist. is intended to provide.

Therefore, the timer control method in the data processing system of the present invention has a plurality of processing units equipped with program memories storing predetermined processing means, and the processing units are configured to perform the following processing when a predetermined time elapses from a predetermined time. In a data processing system configured to move to a processing step, a timer means for counting the specified predetermined time; a memory means for storing information for identifying a processing unit that has specified the predetermined time; is provided in one or more processing units, and information that generates in each processing unit identification information indicating that the processing unit specifies the timer means of other processing units and time information specifying the predetermined time. a generating means, a table means for storing step designation information indicating the next processing step in correspondence with the identification information, and a table means connected to another processing unit to transmit information generated by the information generating means to the other processing unit. The processing unit is characterized in that a timer means of the processing unit is configured to measure the predetermined time.

Hereinafter, the present invention will be explained with reference to the drawings.

1a and 1b are block diagrams and explanatory block diagrams of one embodiment of the present invention, in which A and B are microprocessors;
1 to 4 are output registers, 5 to 8 are input registers, 9 is a jump table, and 10 and 11 are ink face signal lines, respectively.

Further, CM1 and CM2 are control memories in which processing procedures such as timer subroutines and other processing programs are stored, and PU1 and PU2 are instruction execution units that execute instructions stored in the control memories CM1 and CM2 in a predetermined order. What is read and executed with IP1~
5 is an input/output port that outputs an interrupt to the instruction execution unit PU at a predetermined timing, and CG (13) is a clock generator that outputs to the input/output port IP4 every 4 msec to raise an interrupt. It is.

Further, each input/output port (P5, (2)P6 is connected to various types of input/output devices, and generates control signals for operating each input/output device in accordance with output data.

Next, the operation of the real leprosy train of the present invention will be explained.

When the instruction execution unit I-PU of the microprocessor A is executing a general processing routine among the programs in the control memory CM, when the processing routine requests a timer subroutine, an instruction called jump subroutine timer is executed.

In this instruction, the instruction execution unit searches the jump table 9 for an unused timer and outputs the unused timer number.

As a result, the timer number is set to the output register 1 of the input/output port P1, the timer value is set to the other register 2 of the input/output port IP1 of the microprocessor A, and the contents of these registers 1 and 2 are transferred to the interface 10.
Microprocessor B input/output port ■P2 via
The data is sent to input registers 5 and 6 located inside.

The timer numbers are stored in the jump table 9 with "71,""72," and "73," for example.

Note that "7" indicates the address of the own processor and a timer service request, and "1" indicates the timer identification.

If it is the second timer service request, the timer number is, for example, "72".

When data is set in the input registers 5 and 6, an interrupt is generated from the input/output port IP2 to the instruction execution unit PU2, and the instruction execution unit PU2 of the microprocessor B senses the states of the registers 5 and 6.

Then, seeing the timer number "71", it knows that it is a timer service request, and executes the timer subroutine.

In other words, set the timer number "71" to the timer table memo 1.
At the same time, the timer value of timer number "71" is set in a predetermined area of the memory 12, and the output port ■P4 generated by the timing clock generated from the clock generator 13 is saved every time an interrupt occurs. That is, the contents of the area are subtracted by 1 every unit time.

Incidentally, assuming that the timer area in the memory 12 of microprocessor B is for n timers, for example, the lower bit of the timer number, for example, the number "1" in the timer number "71"
'' is determined as one of the timer areas in microprocessor B.

When the contents of the above area become zero, the instruction execution unit PU
2 determines this and then sees the timer number "71" and recognizes that this timer request is from microprocessor A, and sends the timer number "71" to the output register of input/output port ■P2. Set to 3.

The contents of the output register 3 are sent to the input register 7 via an interface signal 11.

When data is set in the input register 7 of the input/output port IP1, an interrupt occurs in the instruction execution unit PU1, the contents of the input registers 7 and 8 are sensed, and interrupt processing is performed.

Since "71" is set in the input register 7, the interrupt processing routine knows that this is a time-up response to a timer service request, and indexes the jump table 9 using the lower digits of the timer number.

As a result, the jump destination addresses H1 and L2 are read out.

Jump destination address H1, L2 is timer number “71”
This indicates the start address of the time-up processing routine to be executed when the time-up occurs.

When the first addresses H1 and L1 are designated, time-up processing corresponding to the timer number is performed.

For example, the timer number set in the input register T is “7”.
2”, jump address table 9 H
2, L2 is read.

Note that when microprocessor A requests timer service from microprocessor B, the timer number and jump destination addresses H and L are entered in the jump table 9.

As is clear from the above description, according to the present invention, a timer subroutine can be shared by a plurality of microprocessors, thereby reducing memory capacity.

[Brief explanation of the drawing]

FIGS. 1a and 1b are a block diagram and an explanatory diagram of one actual case of the present invention. A and B...Microprocessor, 1 to 4.
...Output register, 5 to 8...Input register, 9...Jump address table, 10 and 11...Ink face signal line.

Claims (1)

[Claims] 1 A data processing system having a plurality of processing units equipped with a program memory storing predetermined processing means, and the processing units are configured to move to the next processing step when a predetermined time has elapsed from a predetermined time. In,
One or more processing units are provided with timer means for counting the specified predetermined time and memory means for storing information for identifying the processing unit that has specified the predetermined time, and each processing unit is provided with: information generating means for generating identification information indicating that the processing unit designates the timer means of another processing unit and time information specifying the predetermined time; and information generation means for generating the next processing step in response to the identification information. and input/output means connected to another processing unit to transfer information generated by the information generation means to the other processing unit,
1. A timer control method in a data processing system, characterized in that a processing unit causes a timer means of another processing unit to measure the predetermined time.