JPS589519B2 - semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only memory circuit (hereinafter referred to as ROM) in a MOS type semiconductor device.

) related to higher integration density and larger capacity.

An example of a ROM in a conventional MOS type semiconductor device is the first one.
As shown in the figure, the number of X inputs is n from AX1 to AXn, and the number of Y inputs is A.
It has a single cell from Yt to AYm and L pieces from 1 to OL, and is composed of a memory cell 1, an X address decoder circuit 2, a Y address decoder circuit 3, and a buffer circuit 4.

FIG. 2 is a circuit diagram of the memory cell 10 in FIG. 1, which is composed of a plurality of resistors R and a MOS FET 5.

Xo-XS is the output of the X address decoder circuit 2, and only one output line is selected to the "H" level by the address inputs AX+ to AXn, and all other output lines are "H" level.
It becomes L″ level.

When the output line of the X address decoder circuit selected as “H” level is connected to the gate electrode terminal of the MOS FET, a current flows from the drain electrode terminal of the MOS FET to the grounded source electrode terminal via the resistor R. The data line connected to the drain electrode terminal is “L”
become the level.

For example, in Figure 2, the output line X of the X address decoder circuit
1 is "H" level and the other output line X.

, X2 to Xs are selected as "L" level, data lines 1, 3, and 5 are set to "L" level, data lines 2, 4,
becomes “H” level.

FIG. 3 is an element layout diagram when the memory cell circuit of FIG. 2 is implemented in an integrated circuit device.

6 is a diffusion layer formed in the output line, 7 is each MOS FE
9 is an oxide film forming the gate electrode terminal of the MOS FET, 10 is an aluminum wiring connecting each oxide film 9, and 11 is a gap separating the data lines. It is.

As shown in FIG. 3, conventionally, a gap 11 separates data lines, but there are no passive or active elements directly under the gap, and it is just a space for wiring.

In conventional large-capacity ROM structures, this space occupies a large proportion, which contributes to an increase in chip size and has the drawback of making it difficult to achieve high integration density of ROMs.

As a prior art that avoids the above-mentioned drawbacks, Japanese Patent Application Laid-Open No. 51-5
There is No. 0617.

In this prior art, adjacent data output lines are made common (unified), a ground line is placed on both sides of the line, and a set of MIS FETs is placed between this ground line and the common data output line. It is obtained by

However, this prior art requires two MIS per bit.
}Since it is composed of transistors, it still has the disadvantage that the area occupied by the memory cell is quite large.

As is well known, in a memory circuit such as a read-only memory (ROM) made of a semiconductor integrated circuit, the storage section, that is, the ROM cell group, usually occupies more than 70% of the entire integrated circuit chip.

Therefore, based on the fact that an efficient element layout and minimizing the number of elements per cell contributes to a significant increase in the degree of integration, the present invention provides a memory that simultaneously satisfies both of the above. This circuit was developed for the purpose of obtaining a circuit, and its feature is that any one of the addresses of the address decoder circuit is used for selecting the ground line of the memory cell, which will be described in detail below.

FIG. 4 is an embodiment of the present invention, and is a configuration diagram of a semiconductor memory circuit in which any one input signal of the X address of the X address decoder circuit, for example, the maximum digit input AXn, is used for selecting the ground line of the memory cell. , FIG. 5 is a diagram showing an embodiment of the present invention, showing a memory cell of a dynamic type memory circuit using complementary field effect transistors (hereinafter abbreviated as CMOS).

In Figure 5, 20 is a MOS FET, 31, 33, 3
5, 37, 39, 42 are P-channel MOSFETs that are turned on when the gate voltage is at "L"level; 30, 32, 34
, 36, 38, 40, 41, 43, the gate voltage is ``H''
It is an N-channel MOS FET that turns on when the level is high.

44 and 45 are AND logic circuits, and 46 is an inverter circuit, which are operated by the clock signal φ and any one input signal of the X address decoder circuit, for example, the maximum digit input signal AXn.
As shown in the operation time chart of FIG. 6, φ1 and φ2 signals are obtained, and the P and N channel MOS FETs 30 to
The signal is input to the gate electrode terminal 43.

When clock signal φ is at “L” level, P channel MOS
FET31, 33, 35, 37, 39, 42 are turned on, and N-channel MOS FET30, 32, 34,
36, 38, 40, 41, and 43 are turned off, so each data line is connected to the power supply VDD.

Therefore, all the data lines are charged to VDD, that is, the "H" level, so the data becomes INVALID.

When the clock signal φ is at "H" level, the above state is reversed and the P-channel MOS FETs 31, 33, 36, 37
, 39, 42 are off-operated, and the N-channel MOS FE
T30, 32, 34, 36, 38, 40, 41, and 43 are turned on half by the maximum digit input signal AXn, the data line and power supply VDD are cut off, and the data is in the VALID state.

If the clock signal φ is now at “H” level and the maximum digit input signal AXn of the X address decoder circuit is at “L” level, then φ
1 becomes "L" level and N channel MOS FET3
0, 34, 38, and 41 are turned off, and each drain electrode terminal is separated from the ground, so the MOS FET 20 connected to these terminals becomes ineffective.

Also, φ2 becomes “H” level, and N-channel MOS F
Since ET32, 36, 40, and 43 are turned on and each drain electrode terminal is grounded, the MO connected to this terminal
S FET20 is enabled, and the X address output terminal X of the X address decoder circuit.

-Xs is at the "H" level, and if a MOSFET is connected to this output terminal, the MOSFET is turned on, the data line is grounded, and the "L" level is output.

Also, if no MOS FET is connected to the output terminal of the X decoder, the data line holds the "H" level.

If the clock signal ψ is at the "H" level and the maximum digit input signal AXn of the X address decoder circuit is at the "H" level,
Since φ1 is at the "H" level and φ2 is at the "L" level, the operation is opposite to that described above.

That is, N channel MOS FET30, 34, 38, 4
1 is turned on and each drain electrode terminal is grounded, so the MOS FET 20 connected to this terminal is enabled, and when any one of the output terminals xo-Xs of the X address decoder circuit is at the "H" level, MO at its output terminal
If the SFET is connected, the data line is grounded and the "L" level is output.

Also, if no MOS FET is connected to the X decoder output terminal, the data line holds the "H" level.

FIG. 7 is an element layout diagram in which the memory cell circuit of FIG. 5 is implemented in an integrated circuit device.

47 is a diffusion layer forming data lines DATA-DATAK formed on a semiconductor substrate (not shown); 48 is a diffusion layer disposed on both sides of this diffusion layer 47; Channel MOS FET
N-channel MOS FETs 30, 32, 34, 36 whose sources are connected to the source terminal of 20 and the ground line 51
, 38, 40, 41, and 43.

52N is an oxide film forming the gate of the N-channel MOS FET 20, 53 is an aluminum wire connected to each oxide film 52 of the N-channel MOSFET 20, 54 is an aluminum wire connected to the output of the AND logic circuit 44, and 55 is an aluminum wire connected to the output of the AND logic circuit 44; Aluminum wiring is connected to the output of the logic circuit 45, and 56 is a diffusion layer 47 forming a data line and a P-channel MOS F.
The aluminum wiring 57 connecting each drain of ET31, 33, 35, 37, 39, 42 is an AND logic circuit 44,4
Aluminum wiring connected to the clock signal input to 5,
58 is an aluminum wiring connected to the power supply potential VDD; 50 is an aluminum wiring connected to the power supply potential VDD;
P channel MOS FET31, 33, 35, 37,
P-type diffusion layer forming each drain of 39, 42, 49 is P-channel MOS FET 31, 33, 35, 37, 39
, 42, and 52P is a P-channel MOSFET 31, 33, 35, 37, 39, 42.
This is the oxide film that forms the gate.

As explained above, according to the present invention, an efficient element layout is obtained by arranging MOS FETs on both sides of the data line, and furthermore, an arbitrary signal of the X or Y address of the address decoder circuit can be used to connect the data line. MOS FET on the right or left side of the ground line selection MOS FE
By switching with T and reading data, one bit of ROM can be realized with one MOS FET, so when designing a large-capacity ROM, an increase in chip size can be prevented.

Also, the benefit of using any one address of the address decoder circuit for selecting the ground line of the memory cell is that if the number of inputs to the address decoder circuit is n, the number of outputs is 2n. Therefore, as a result of subtracting the address of the ADLS decoder circuit by one, that is, setting the number of inputs to n-1, the number of outputs becomes 2n-1, and the number of outputs becomes 1/2.

This reduces the area of the memory cells by about half, so the chip size can be significantly reduced.

Furthermore, since the memory circuit of the present invention is constructed of CMOS, no power is consumed due to load resistance during operation.

Therefore, it has the feature of requiring extremely low power consumption.

The present invention is extremely effective for applications in peripheral circuits such as calculators, character generators, and microprocessors.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional read-only memory circuit;
Fig. 2 is a circuit diagram of the memory cell in Fig. 1, Fig. 3 is an element layout diagram that is an integrated circuit of Fig. 2, Fig. 4 is a configuration diagram of a glue-only memory circuit of the present invention, and Fig. 5 is a circuit diagram of the memory cell shown in Fig. 1. A circuit diagram of a dynamic type memory cell using complementary field effect transistors, which is a memory cell of the invention, FIG. 6 is an operation time chart of the gate circuit shown in FIG. 5, and FIG. FIG. 2 is an element layout diagram in which the figure is integrated circuit. 20...MOS FET, 30, 32, 34, 36, 3
8, 40, 41, 43...N channel MOS, 31,
33, 35, 37, 39, 42...P channel MOS
, 44, 45...AND circuit, 46...Inverter circuit, 47, 48, 49, 50...=diffusion layer, 51...stomach ground line, 52N, 52P...gate oxide film, 53, 54,
55, 56, 57, 58m...Aluminum wiring.

Claims (1)

[Claims] 1. In a memory circuit in which a read-only memory cell is configured by a plurality of MOS FETs on a semiconductor substrate, a plurality of decoder outputs connected to an address decoder circuit and a plurality of first conductivity type a second diffusion layer of the first conductivity type disposed on both sides of the first diffusion layer of the first conductivity type; a second diffusion layer of the first conductivity type and the second diffusion layer of the first conductivity type; at least one first channel type IMOS FET formed between the first and second diffusion layers and having a gate connected to a selected decoder output of the plurality of decoder outputs; a plurality of second channel type MOS FETs connected to one end of each of the first diffusion layers, having a source connected to the first power supply potential, and a gate to which a clock signal is input;
A memory cell and a peripheral portion are configured including a first channel type second MOS FET having a drain connected to the first conductivity type second diffusion layer and a source connected to a second power supply potential, and the address decoder The second MOS of the first channel type performs a logical product of one of a plurality of address signals input to the circuit and the clock signal.
The signal is input to the odd (or even) gate of the FET, and the AND of the inverted signal of the arbitrary address signal and the clock signal is input to the even (or odd) gate of the second MOS FET of the first channel type. A semiconductor memory circuit characterized in that it is connected and configured for input.