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JPS589579B2 - Hand Thai Souchino Seizou Souchino - Google Patents
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JPS589579B2 - Hand Thai Souchino Seizou Souchino - Google Patents

Hand Thai Souchino Seizou Souchino

Info

Publication number
JPS589579B2
JPS589579B2 JP13932674A JP13932674A JPS589579B2 JP S589579 B2 JPS589579 B2 JP S589579B2 JP 13932674 A JP13932674 A JP 13932674A JP 13932674 A JP13932674 A JP 13932674A JP S589579 B2 JPS589579 B2 JP S589579B2
Authority
JP
Japan
Prior art keywords
wafer
souchino
wafers
seizou
thai
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13932674A
Other languages
Japanese (ja)
Other versions
JPS5164867A (en
Inventor
安田興光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP13932674A priority Critical patent/JPS589579B2/en
Publication of JPS5164867A publication Critical patent/JPS5164867A/en
Publication of JPS589579B2 publication Critical patent/JPS589579B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 この発明は、半導体ウエハーを熱処理して作製される半
導体装置の製造装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for manufacturing a semiconductor device manufactured by heat treating a semiconductor wafer.

半導体装置は、主にシリコンの単結晶ウエハーでもって
作製されているが、こうしたシリコン半導体装置の製造
過程には熱処理や光食刻等の高度に精密なる制御が要求
される工程が含まれているとりわけ熱処理工程では、シ
リコンウエハーの結晶性が不純物の拡散時あるいは表面
酸化時に損われることがしばしばあり、この問題につい
ては種種にその原因が指摘されてきている。
Semiconductor devices are mainly manufactured using single-crystal silicon wafers, and the manufacturing process for these silicon semiconductor devices includes processes that require highly precise control, such as heat treatment and optical etching. Particularly in heat treatment steps, the crystallinity of silicon wafers is often impaired during diffusion of impurities or surface oxidation, and various causes of this problem have been pointed out.

シリコンウエハーの結晶性が損われる原因は、犬別して
以下の点にある。
The causes of loss of crystallinity of silicon wafers are as follows.

すなわち、(1) シリコンウエハー自体を製作する
工程、つまり単結晶シリコンのインゴットを作るとき、
あるいはその後にスライシングによって所定厚のウエハ
ーを得るときの加工歪により発生する結晶欠陥。
In other words, (1) the process of manufacturing the silicon wafer itself, that is, when making the single-crystal silicon ingot,
Or crystal defects that occur due to processing strain during subsequent slicing to obtain a wafer of a predetermined thickness.

:2)熱処理時の加熱炉による昇温、降温の過程で発生
する歪。
:2) Strain that occurs during the process of temperature rise and fall in the heating furnace during heat treatment.

(3)拡散時に拡散不純物原子がその種類あるいは濃度
に応じてひきおこす結晶欠陥。
(3) Crystal defects caused by diffused impurity atoms depending on their type or concentration during diffusion.

などである。etc.

そしてこれらの点については、無転位単結晶を用いたり
((1)への対処)、熱応力の発生を防ぐために徐熱徐
冷を行なったり((2)への対処)、拡散濃度を低くし
て行なう完全結晶技術(PCT)が使用される((3)
への対処)。
Regarding these points, we can use dislocation-free single crystals (to deal with (1)), perform slow heating and cooling to prevent the occurrence of thermal stress (to deal with (2)), and reduce the diffusion concentration. Perfect crystal technology (PCT) is used ((3)
).

しかして、上記の点と同様に重要なことは、加熱処理時
にシリコンウエハーを支持する装置いわゆるウエハーボ
ートがウエハーの結晶性に及ぼす影響である。
However, just as important as the above points is the effect that a so-called wafer boat, a device that supports silicon wafers during heat treatment, has on the crystallinity of the wafers.

第1図は現在使用されているウエハーボートの一例で、
ボート本体1は炭化珪素や石英で形成した枠体をなして
いて、平行する2辺の枠体に一定の間隔でウエハーを垂
直に保持する案内溝が設けられるものである。
Figure 1 shows an example of a wafer boat currently in use.
The boat body 1 has a frame made of silicon carbide or quartz, and guide grooves for vertically holding wafers are provided at regular intervals on two parallel sides of the frame.

第2図は上記ウエハーボートを第1図1−1線に沿う断
面で示した図で、シリコンウエハー2が案内溝に支えら
れて直立に保持されている。
FIG. 2 is a cross-sectional view of the wafer boat taken along line 1-1 in FIG. 1, in which silicon wafers 2 are supported by guide grooves and held upright.

この場合、上記案内溝とウエハー2の接触状態は面接触
であって、この状態で熱処理されるとこの接触部のシリ
コンウエハー2が結晶欠陥を発生しやすくなる。
In this case, the contact state between the guide groove and the wafer 2 is a surface contact, and if the silicon wafer 2 is heat-treated in this state, crystal defects are likely to occur in the silicon wafer 2 at this contact portion.

第3図a,bおよび第4図a,bも通常使用されている
ウエハーボートであり、第1図のものと同様保持される
ウエハー2はいずれもボートの案内溝で面接触する構造
となっていて、上述した結晶欠陥が発生し易い点では同
じである。
3a, b and 4 a, b are also commonly used wafer boats, and like the one in FIG. 1, the wafers 2 held are both structured so that they make surface contact in the guide groove of the boat. However, it is the same in that the crystal defects described above are likely to occur.

すなわちウエハーとボートが接触している箇所では、後
にこのウエハーをチップに分割して半導体装置としてテ
ストすると、不良品になっている確率が高くなるという
欠点があった。
In other words, at the point where the wafer and the boat are in contact, there is a drawback that if the wafer is later divided into chips and tested as a semiconductor device, there is a high probability that the product will be defective.

この発明は、上記の点に鑑みてなされたもので、?熱炉
中などに半導体ウエハーを保持するとき、このウエハー
が点あるいは線接触状態で垂直に保持できる半導体装置
の製造装置を提供することを目的とする。
This invention was made in view of the above points. An object of the present invention is to provide a semiconductor device manufacturing apparatus that can hold a semiconductor wafer vertically in point or line contact when the wafer is held in a thermal furnace or the like.

以下図面を参照してこの発明の一実施例を説明する。An embodiment of the present invention will be described below with reference to the drawings.

第5図は垂直に保持された半導体ウエハー12の側面図
である。
FIG. 5 is a side view of semiconductor wafer 12 held vertically.

上記ウエハー12は、このウエハー12の周縁部に接す
る位置に水平に配置された4本の断面円形の棒状部材1
1,112113,114からなる支持用枠体11によ
って保持されるもので、ウエハー12の重量を支える底
部に配置した2本の下方位置棒状部材11、,11と側
部に配置した2本の下方位置棒状部材113,?1,と
はそれぞれ互いに平行になっている。
The wafer 12 has four rod-shaped members 1 each having a circular cross section and which are horizontally arranged in contact with the peripheral edge of the wafer 12.
It is held by a supporting frame 11 consisting of 1, 112, 113, 114, and is supported by two lower rod-shaped members 11, , 11 placed at the bottom that support the weight of the wafer 12, and two lower rod members 11 placed on the sides. Position rod-shaped member 113,? 1 and are parallel to each other.

第6図は上記枠体11と2枚のウエハー12,122の
平面配置図である。
FIG. 6 is a plan view of the frame 11 and two wafers 12, 122.

側部の棒状部材11,,11,に切欠形成されたV字状
の案内溝13、,13,13,132は、上記ウエハー
12,12が各案内溝13 ,13 ,13,13
の内壁面と点接触状態となるように、切欠角度が15°
〜60°の間の値が選択されている。
The V-shaped guide grooves 13, , 13, 13, 132 formed in the side rod-shaped members 11, , 11, are arranged so that the wafers 12, 12 can be inserted into the respective guide grooves 13, 13, 13, 13.
The notch angle is 15° to make point contact with the inner wall surface of
Values between ˜60° have been chosen.

また、底部の部材11 .11 とウエハー12
.12とは面接触ではなくて線接触状態となっている
Also, the bottom member 11. 11 and wafer 12
.. 12 is not in surface contact but in line contact.

なお、上記各棒状部材の材質は、石英である。In addition, the material of each of the above-mentioned rod-shaped members is quartz.

上記実施例の構成であれば、半導体ウエハー12は案内
溝13内で点接触、ウエハーの重量を支える底部の部材
11,112では線接触となる.?なわち、ウエハー1
2 .12の重量は全て2本の下方位置棒状部材11
.11に作用し、かつ丸棒の外周に直角に線接触と
なる。
With the configuration of the above embodiment, the semiconductor wafer 12 makes point contact within the guide groove 13, and line contact occurs at the bottom members 11 and 112 that support the weight of the wafer. ? That is, wafer 1
2. The weight of 12 is entirely due to the two lower rod-shaped members 11
.. 11 and is in line contact at right angles to the outer periphery of the round bar.

したがって側方位置棒状部材113,114の案内溝1
3,13.13,13は、単にウエハー12,122の
傾動を阻止すればよいので大きな応力は作用せず両者は
点接触状態で安定にウエハー12、,12を保持するこ
とができる。
Therefore, the guide groove 1 of the side rod-shaped members 113, 114
3, 13. 13, 13 only need to prevent the wafers 12, 122 from tilting, so that no large stress is applied and the wafers 12, 12 can be stably held in point contact between them.

したがって、加熱処理時にこうした枠体11でウエハー
を支持すれば、結晶性が損なわれるなどの影響はほとん
ど防ぐことができる。
Therefore, if the wafer is supported by the frame 11 during heat treatment, effects such as loss of crystallinity can be almost prevented.

次表には、上記構成の装置と従来装置(第1図)とを用
いて加熱処理した後に、半導体ウエハー表面をエッチン
グしてその欠陥を評価した結果が示されている。
The following table shows the results of etching the semiconductor wafer surface and evaluating its defects after heat treatment using the apparatus having the above configuration and the conventional apparatus (FIG. 1).

エッチング液はC r Os十HFを使用し、各装置で
のウエハーは同一デザインで同一ピッチとし、加熱条件
も一定としていることはもちろんである。
The etching solution used was C r Os HF, the wafers in each device had the same design and the same pitch, and it goes without saying that the heating conditions were also constant.

すなわち速度30秒では本案装置、従来装置ともシリコ
ンの結晶性が損なわれ、生産歩留りの向上も明日とはな
りがたいが、本案装置では速度2分以上の場合に欠陥は
まったく発生していない。
That is, at a speed of 30 seconds, the crystallinity of silicon is impaired in both the device of the present invention and the conventional device, and it is difficult to expect an improvement in production yield, but with the device of the present invention, no defects occur at all at speeds of 2 minutes or more.

なお、上記の表において昇温・降温速度とは上記各装置
をそれぞれ加熱炉内に挿入する時、炉の入口部から所定
温度に達している炉中心部(4敗功までに達するに要す
る時間を示している。
In addition, in the table above, the temperature increase/decrease rate refers to the time required to reach the specified temperature from the inlet of the furnace to the center of the furnace (up to 4 failures) when each of the above devices is inserted into the heating furnace. It shows.

この速変は、熱処理効率からいえば速い方がよいが、一
投には温度変化が急激であればある程結晶欠陥の発生す
る機会が多くなっている。
In terms of heat treatment efficiency, the faster the speed change, the better, but the more rapid the temperature change in one throw, the more opportunities for crystal defects to occur.

以上この発明によれば、半導体装置の製造工程のうち加
熱処理時に複数枚の半導体ウエハーを同時に保持するの
に、点あるいは線接触状稗で支え、塾処理によるウエハ
ーの結晶欠陥の発生を抑え、半導体装置の歩留向上に寄
与するとともに加熱処哩そのものを効率的に行ないつる
半導体装置の製へ装置を提供できる。
As described above, according to the present invention, a plurality of semiconductor wafers are simultaneously held during heat treatment in the manufacturing process of semiconductor devices by supporting them with a point or line contact shape, thereby suppressing the occurrence of crystal defects in the wafers due to cram treatment, and It is possible to provide an apparatus for manufacturing semiconductor devices that contributes to an improvement in the yield of semiconductor devices and efficiently performs the heat treatment itself.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の半導体ウエハー用のボート
の一例を示す図、第3図a,bは従来のボートの他の一
例を示す図、第4図a,bはさらに他の一例を示す図、
第5図はこの発明装置の一夷施例を示す側断面図、第6
図は同実施例の平面図である。 11〜114・・・・・・断面円形の棒状部材、12
1?22・・・・
・・半導体ウエハー、13,132・・・・・・案内溝
Figures 1 and 2 are views showing an example of a conventional boat for semiconductor wafers, Figures 3a and b are views showing another example of a conventional boat, and Figures 4a and b are still another example. A diagram showing
FIG. 5 is a side sectional view showing one embodiment of the device of the present invention, and FIG.
The figure is a plan view of the same embodiment. 11-114... Rod-shaped member with circular cross section, 12
1?22...
...Semiconductor wafer, 13,132...Guide groove.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体ウエハーを立体で複数枚同時に炉内に保持す
る半導体装置の製造装置において、ウエハー周縁の下方
に位置してウエハーの自重を支える互いに平行な2本の
下方位置棒状部材と、ウエハー周縁の両側に位置してそ
れぞれ内側に15°〜600に切欠した複数のv字状の
案内溝を軸方向に複数有しかつ上記案内溝壁でウエハー
を点接触状態で保持する2本の側方位置棒状部材とを具
備する半導体装置の製造装置。
1. In a semiconductor device manufacturing apparatus that holds a plurality of three-dimensional semiconductor wafers in a furnace at the same time, two downwardly positioned rod-like members parallel to each other are located below the wafer periphery and support the weight of the wafer, and two downwardly positioned bar-like members are placed below the wafer periphery to support the wafer's own weight; two lateral rod-shaped rods each having a plurality of V-shaped guide grooves in the axial direction and each having a plurality of V-shaped guide grooves cut out at an angle of 15° to 600° on the inside, and holding the wafer in point contact with the guide groove walls; A semiconductor device manufacturing apparatus comprising:
JP13932674A 1974-12-03 1974-12-03 Hand Thai Souchino Seizou Souchino Expired JPS589579B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13932674A JPS589579B2 (en) 1974-12-03 1974-12-03 Hand Thai Souchino Seizou Souchino

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13932674A JPS589579B2 (en) 1974-12-03 1974-12-03 Hand Thai Souchino Seizou Souchino

Publications (2)

Publication Number Publication Date
JPS5164867A JPS5164867A (en) 1976-06-04
JPS589579B2 true JPS589579B2 (en) 1983-02-22

Family

ID=15242695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13932674A Expired JPS589579B2 (en) 1974-12-03 1974-12-03 Hand Thai Souchino Seizou Souchino

Country Status (1)

Country Link
JP (1) JPS589579B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599719A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Heat treatment jig of wafer
JPS58138918U (en) * 1982-03-12 1983-09-19 中興化成工業株式会社 Support device for cleaning lenses, etc.
JPS59125838U (en) * 1983-02-10 1984-08-24 ホ−ヤ株式会社 board storage box
JPS63257217A (en) * 1987-04-15 1988-10-25 Hitachi Ltd Heat treatment jig
JPH0648825Y2 (en) * 1987-07-23 1994-12-12 富士通株式会社 Wafer carrier for growth equipment

Also Published As

Publication number Publication date
JPS5164867A (en) 1976-06-04

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