JPS5910070B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for a logic circuit, and provides a structure suitable for reducing power consumption.

Several semiconductor devices for logic circuits have been known in the past, one of which is the highly integrated I2L (In
A logic circuit element having a tegrated injection logic structure is well known, as shown in Japanese Patent Publication No. 49-35030, for example. This I2L has the features of lower power consumption and higher density than conventional bipolar elements. The applicant has improved the shortcomings of I2L,
Patent application for an element with a new structure that exceeds the performance of I2L
It was proposed in No. 5095.

This has a structure equipped with a switching element of a new structure, and any number of fanouts can be freely taken out.
The object of the present invention is to provide a logic circuit element having a small speed-power product and a small element area. First, the device with this new structure will be described in detail. FIG. 1A is a partial schematic plan view of the same element, FIG. 1B is a partial schematic sectional view taken along the line XX' shown in FIG. 1A, and FIG. It is a partial schematic sectional view when cut|disconnected by YY' shown in FIG. A.

In FIG. 1, reference numeral 1 denotes an n+ type substrate having a low resistivity, for example, about 0.001 Ωm, and is kept at ground potential.

2 is an n-type layer formed on the above 1 and having a high resistivity, for example, about 50 JΩm.

3 and 4 are p+ type regions formed from the surface of 2,
Said 3 and 4 are arranged close to each other, and said 3 is said 2
The area is formed, for example, in a mesh shape so as to partially surround the area.

PnP transistor and star T1 composed of the above 4, 2, and 3
4, 2, and 3 are an emitter, a base, and a collector, respectively. Further, a part 2' of the region 2 surrounded by the above 3 is formed so that it is filled with a depletion layer due to the diffusion potential of the Pn junction composed of the above 3 and γ when the potential of the above 3 is ゛O''V. be done.

5 is an n+ type region formed on the surface of 2, and 1, 3
, 2', and 5, 3 serves as a gate, and 1, 2', and 5 serve as conductive paths.

Terminal 4 is used as bias terminal b, terminal 3 is used as input terminal 1, and terminal 5 is used as output terminal 0.The operation will be explained next.A current IB is always injected from terminal b.

If the terminal 1 is now in a floating state, the potential of the collector of the transistor T1, that is, the gate 3 of the transistor T2 increases to approximately +0.6V due to holes injected from the emitter 4 of the transistor T1. For this reason, switching element S1
There is almost no depletion layer in the conductive path region 2' of 1-
A conductive path 2'-5 is formed, and the output of terminal 0 is ``O
``V. Next, terminal 1 is at ground potential, that is, 10゛V.
When this happens, the holes accumulated in the gate 3 of the switching element S1 are discharged through the terminal 1, and the gate 3 becomes 0V.
becomes. Therefore, the conductive path region 2' of the switching S1 is
As described above, due to the diffusion potential generated at the Pn junction between gate 3 and region 2', it is filled with a depletion layer, and terminals 2 and 5 are electrically separated and terminal 0 is in a floating state. In this way, transistor T1 and switching element S1 form an inverting circuit. Although the device structure described above has better performance than the conventional IIL, it has the following problems.

(1) Considering the operating principle and structure of the above element, the base region of the lateral PNP transistor T includes a low concentration n region made of the n-type layer 2, so there is a punch-through between the emitter and collector of the PNP transistor. It is necessary to increase the base width to prevent this from occurring.

Therefore, high density is lost. For example, base concentration 1014a
If t0ms1cr1, the base width needs to be 5.3μ or more so that the depletion layer is not filled with the diffusion potential.
(2) As the base width increases, the current amplification factor of the PNP transistor decreases, which is disadvantageous in terms of power consumption.

In addition, in order to overcome the above-mentioned drawbacks, there is a double epitaxial method in which a higher concentration epitaxial layer is formed on a lower concentration epitaxial layer, but this method is complicated due to process complexity and PNP transistor From the point of view of increasing the current amplification factor of T1, it is not possible to achieve a sufficient effect.

The present invention provides a semiconductor device which satisfies lower power consumption and higher density than the previously applied switching element having a new structure. An embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3. [For example, a resistivity of about 500 is applied to the single-crystal Sl substrate 11, which is a highly concentrated n-type layer.
(Deposit an n-type single crystal layer 12 of -m.

[B] An n-type impurity such as phosphorus is diffused into the n-type single crystal layer 12 using the insulating film 13 such as SiO2 as a mask.

The n-type layer 14 formed at this time is formed by diffusion from the window 15, forms part of the base region of the lateral PNP transistor, and has a higher impurity concentration than the n-type epitaxial layer 12. . Note that ion implantation may be used when forming this n-type layer 14. [C] In step [B], mask windows 16 are further opened in the insulating film 13, leaving the mask windows 15 in which the n-type layer 14 is formed as they are.

P-type layers 17 and 18 are formed through these insulating film openings 15 and 16 using boron thermal diffusion and ion implantation.
The P-type layers 7 and 8 become the emitter and collector of the lateral PNP transistor, respectively. 1] Highly concentrated n-type layer 19 using thermal diffusion or ion implantation of phosphorus or arsenic
form.

(6) Form the extraction electrode 20 using Al as an electrode.

FIG. 3 is a plan view of the main part of FIG. 2D with the insulating film 13 removed.

In the switching element according to the present invention, in FIG. 2(F)), 17 serves as the emitter or injector of the PNP transistor T1, 18 serves as the collector of the PNP transistor and the gate of the switching element, and 14 serves as the PNP transistor T1.
A portion of the base region of the transistor, 19, serves as the output of the switch element S,.

The semiconductor device and its element of the present invention can produce the following effects.

(a) n in the active base region of PNP transistor T1
Since the n-type layer 14 is formed with a higher concentration than the type epitaxial layer 12, punch-through between the emitter and collector of the PNP transistor can be prevented even if the base width is narrowed. Since the area can be narrowed, high density can be achieved.

(b) The current amplification factor of the PNP transistor T1 can be increased due to the drift field effect caused by the narrowing of the base width and the concentration gradient in the base region from the emitter to the collector.

Therefore, it is effective in reducing power consumption as a switching element. (c) Self-alignment can be achieved because the impurities of indie and base are diffused through the same mask hole 15, and the steps required for this are simple.

(d) Compatibility with other bipolar elements can also be easily satisfied.

As described above, according to the present invention, it is possible to obtain a semiconductor device for logic circuits which has particularly excellent high density and low power consumption.

[Brief explanation of the drawing]

Figure 1A is a plan view of a logic circuit element with a conventional structure;
Figures B and C are cross-sectional views taken along lines A(7) FIG. 3 is a plan view of the main part of FIG. 2D. 1-2'-5... Conductive path, 12...n
Single crystal, 13... Insulating film, 14...
High concentration n-type layer, 15, 16... Window, 17, 18
...P-type layer (emitter, collector), 19...
... High concentration n-type layer, T1 ... PNP lateral transistor, S, ... Switching element.

Claims (1)

[Claims] 1 forming, in a semiconductor substrate having one conductivity type serving as a base region of a lateral transistor, regions of the other conductivity type serving as an emitter region and a collector region of the lateral transistor, spaced apart from each other; a conductive path of one conductivity type that reaches the semiconductor substrate from the surface of at least one of the lateral transistors and is surrounded by the collector region of the lateral transistor, in the collector region of the lateral transistor; a switching element having a collector region of the lateral transistor as a gate region, a conductive path of the switching element being filled with a depletion layer due to a diffusion potential of the gate region,
Impurities in the conductive path of the switching element, which has an impurity distribution such that an internal electric field is generated from the emitter region to the collector region of the lateral transistor, and has an impurity concentration that generates the internal electric field in the semiconductor substrate. A semiconductor device characterized by a concentration higher than that of a semiconductor device.