JPS5910069B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for logic circuits that has a small chip area and speed-power product and can provide an arbitrary number of fan-outs.

Several semiconductor devices for logic circuits have been known in the past, one of which is the 12L (Integrated Injection) which has a high degree of integration and saves device area without requiring an isolation diffusion region or a diffusion resistor.
For example, a logic circuit element with a Logic structure is
It is well known as shown in 5030.

An example of a NOR circuit configured with this structure is shown in FIG. 1, and its basic operating principle will be briefly explained. two Ps
type diffusion regions P1, P2, and P3 are formed in an n-type semiconductor substrate (Ni
) are arranged separated from each other.

This P is the emitter, N2 is the base, P2 is the collector, and the lateral transistor Tl is formed, P1 is the emitter, and Ni
A lateral transistor T with P3 as the base and P3 as the collector
form 3. N2N3 regions within the semiconductor substrate N2, P2, and P3 regions are formed by n-type diffusion. By this Ni
A vertical transistor T2 is obtained, with P2 as the emitter, P2 as the base, and N3 as the collector. Now, transistor T
The operation will be explained regarding i and T2. When a current is applied to the emitter Pi of the transistor Tl, the injected holes are partially collected at the collector P2 of the transistor Tl. This causes the Pn junction between P2 and N2 to be biased in the forward direction, and electrons are injected into P2 from the Ni acting as the emitter of transistor T2. Therefore, when A is connected to a current source and power E1 is left floating, a collector current k flows through transistor T2. However, if a ground potential is applied to E1, then 10 is applied to N of transistor T2.
2 is prevented from flowing across the collector region. PNP transistor T1 thus supplies current to the base of NPN transistor T2, which operates in the opposite direction. At this time, when E1 is in a floating state, the current applied to the PNP transistor T1 flows to the base P2 of the NPN transistor T2, and thus the transistor T2 enters a saturated conductive state. However, when El is connected to ground potential, the current 1 applied to T1 flows through Et and cannot flow to the base of T2. In this case T2 is blocked. Considering the potential developed at the collector of T, T1 and T2 form an inverting circuit. Other transistors T3 and T4
The relationship between transistor T1 and transistor T3 described above is also
The operation is similar to that of . 1) A NOR circuit is formed by these transistors T1 to T4. Regarding the element with the conventional structure shown above, the N1 region is the emitter of the transistor T2 and at the same time the base of the transistor T1, so in order not to reduce the emitter injection efficiency of the transistor T, it is not necessary to make it a high impurity concentration. Not allowed and at most 1616at
0m? /CTn3.

Therefore, the transistor T2 operates as a reverse transistor, and the emitter injection efficiency from N2 to P2 is poor, and the emitter ground current amplification factor HFE is usually very small, 2 to 3. Therefore, it is difficult to obtain a large number of fan-outs from collector N2. Furthermore, in order to prevent further reduction in HFE, the base P2 of the transistor T2 is kept at a relatively low impurity concentration, resulting in a large base resistance and a slow calculation speed. Furthermore, since a reverse drift electric field is generated in the base region of transistor T2, the diffusion time of carrier 3A is long.
Furthermore, minority carrier accumulation time is required, which slows down the calculation speed. Therefore, in order to improve the above-mentioned drawbacks, the present inventors filed a patent application in 1973.
No. 1-49095 proposed a structure equipped with a switching element of a new structure.

This device is a logic circuit element that can be taken out in parallel with any number of four fans and has a small speed-power product and element area. The present invention is based on the invention of the previous Japanese Patent Application No. 51-45095, and further aims to reduce the gate resistance and increase the speed.

Hereinafter, one embodiment of the present invention will be described in detail based on FIG.

In FIG. 2, a is a partial schematic plan view of a device according to an embodiment of the present invention, and FIG. 2 b is a partial schematic sectional view taken along the line XX shown in FIG. 2 a. , FIG. 2c is a partial schematic sectional view taken along YY' shown in FIG. 2a.

In Figure 2, 1 indicates low resistivity, for example 0.001+Ω.
C! ! It is an n-type substrate with a size of about L and is kept at a ground potential.

2 is a high resistivity film epitaxially formed on the above 1, for example, 50Ω. It is an n-type layer.

+3 and 4 are P-type regions formed like the surface of 2 above,
Said 3 and 4 are arranged close to each other, and said 3 is said 2
For example, it is formed in a mesh shape so as to partially surround the area.

In the PnP transistor T, which is composed of 4, 2, and 3, 4, 2, and 3 serve as an emitter, a base, and a collector, respectively. In this transistor T1, the base concentration is low and the emitter and collector concentrations are high in efficiency, so that the rate of holes injected from the emitter reaching the collector is much higher than in the conventional structure. In addition, a part 7 of the region 2 surrounded by the above 3 is filled with a depletion layer due to the diffusion potential of the Pn junction composed of the above 3 and 7 when the potential of the above 3 is 0 nV. It is formed.

5 is an n-type region formed on the surface of 2, and 1, 2,
A switching element S consisting of 3, 7, and 5 is configured.

In the elements S and VC, 3 serves as a gate, and 1, 2, and 5 serve as conductive paths. Reference numeral 6 denotes an insulating region formed at a predetermined depth beyond the surface of the gate 3, excluding the electrode lead-out portion of 3 and the portion facing the base of the transistor T.
This reduces the junction capacitance, increases the response speed, and facilitates the formation of the conductive path 2 and its electrodes.

The 4th terminal is the bias terminal B, the 3rd terminal is the manual terminal 1, and the 5th terminal is the output terminal 0. Next, the operation of this device will be explained.

A current 1B is always injected from the terminal B as in the conventional structure.

If the terminal 1 is now in a floating state, the potential of the collector of the transistor T1, that is, the gate 3 of the switching element S1 increases to approximately +0.6V due to holes injected from the emitter 4 of the transistor T1. Therefore, there is almost no depletion layer in the conductive path region 2 of the switching element S1.
A conductive path of 12'-5 is formed, and the output of terminal 0 is 6
0″V. Next, terminal 1 is at ground potential, i.e. 60″V.
When the voltage becomes V, the holes accumulated in the gate 3 of the switching element S1 are discharged through the terminal 1, and the gate 3 becomes 0.
It becomes V. For this reason, the conductive path region 2 of the switching element S,
As described above, is filled with a depletion layer due to the diffusion potential generated at the Pn junction between gate 3 and region 2', and terminals 2 and 5 are electrically separated and terminal 0 is in a floating state. In this way, the transistor T1 and the switching element S form an inverting circuit. Elements with this structure do not use an inverted transistor structure like elements with conventional structures, and the signal is transmitted to terminal 0 only by opening and closing the gate, so fan-out is arbitrary. It has the advantage of being able to freely select and operate as many as .

Further, the base of each of the transistor T1 and the switching element S1 and the region 2 which becomes a conductive path are made as low in concentration as possible, for example, 1014at0m. It is possible to select approximately -3, and thereby the injection effect of the transistor T1 can be greatly improved. At this time, the maximum dimension d of the channel region 2' is based on the condition that the channel region is completely filled with a depletion layer at a diffusion potential of 0.6, for example, d=2×V? J. ＞l
-[Black, 4 x 5.3 μm.

Furthermore, the switching element S1, which was impossible with the conventional structure,
Since the impurity concentration of the gate 3 can be arbitrarily selected to be high, the gate resistance can be lowered and the effective gate area 3 can be reduced.
Since the other regions are insulator regions 6, the gate junction capacitance can also be reduced, which has the advantage of increasing the calculation speed. In addition, the switching element of this structure operates with a large number of carriers, and there is no carrier accumulation effect or reverse drift electric field effect as in conventional structures, and channel 2
'It can be operated easily and quickly during the process. Furthermore, in the conventional structure, the HFE of the transistor T2 is small, so a large collector current of the transistor T1 is required, but in this structure, the collector current is sufficient to charge the stray capacitance between the gate 3 of the switching element S1 and the conductive paths 2 and 7. Because of this, the power of transistor T3 can be made very small, and
The operation of the switching element S1 is essentially different from the operation of the conventional transistor T2, and it is efficient and can handle a large switching current with a small area, so it also has the advantage that the area of the switching element can be reduced. Next, an embodiment of the method for manufacturing this structural element will be described with reference to FIG.

Low resistivity, for example, 0.001Ω, on n+ type silicon 1, and high resistivity, for example, 50Ω? A substrate is formed by epitaxially forming n+ type silicon 2 (FIG. 3a).

Next, regions 3 and 4 containing a P-type impurity, for example, boron, are formed from the surface of the second layer in a predetermined shape to a depth of about 2 μm by a well-known thermal diffusion method or ion implantation method.

Here, 3 is the collector of the transistor T1 and the gate of the switching element S1. Each region 4 corresponds to the region 2.
A predetermined surface shape, for example, a mesh shape, is formed so as to surround a partial region 7 of
It is formed so that it is almost completely filled with a depletion layer only by the diffusion potential of the Pn junction between the two. Now, the impurity concentration of 2' is 1X1014at0m/? 3 (50 Ω-Cm), the maximum dimension of 2' is approximately 5.3 μm. (Figure 3b). Next, a Si3N4 film 10 is formed on the layer 2 to a thickness of about 1000 Å by, for example, reacting SiH4 and NH3 at a temperature of about 750° C. for several minutes.

Thereafter, the Si3N4 film on the P-type region 4 is removed by a well-known photoetching method except for the gate electrode extraction part and the part facing the base of the transistor T1+, and the opening 11 is removed.
will be established.

Next, silicon etching is performed using the Si3N4 film 1.0 as a mask to form an opening 11VC of 0.6 μm in the substrate.
After forming a concave region with a depth of approximately 1 μm, S
An iO2 film is formed and the recessed area is filled with a SiO2 film 6, so that the surface of the layer 2 is made substantially flat. (Figure 3c). Next, the Si3N4 film 10 on the region surrounded by the region 6 is completely removed by treatment with hot phosphoric acid at about 160° C. for several minutes, and then impurities such as phosphorus that give n-type are removed from the surface of the region 2. A region 5 including the above-described region 6 is formed to a depth of about 0.5 μm within the region surrounded by the region 6 by a well-known thermal diffusion method or ion implantation method.

Here, 5 is an output section of the switching element S1.
Next, after the Si3N4 film 10 is completely removed by the method described above, an SiO2 film (not shown) with a thickness of several thousand amps is formed on the surface of the film 2.

After that, the necessary portions are etched using a well-known photoetching method.
After removing the iO2 film, metal wiring is performed to form regions 3 and 4.
, 5 respectively for the emitter terminal 13 of the transistor T1.
, T1, the gate terminal 14 of the switching element S1, and the output terminal 15 of S1. (Figure 3e).
One or more of the manufacturing methods have excellent characteristics in that the manufacturing process can be easily controlled, the structure of the present invention can be easily realized, and moreover, it can be manufactured in the same process as other bibolar transistors.
As described above, the present invention can provide a semiconductor device for logic circuits that has a small chip area, a small speed-power E product, a small gate capacitance, and is capable of achieving high speed.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of a conventional IIL-structured logic circuit element, and FIG. 2 shows the main parts of the logic circuit element of the present invention, where a is a schematic plan view of the main parts, B and c are B-B', respectively. A sectional view taken along the line C--C and FIGS. 3 a-e are process sectional views showing an example of the manufacturing process of an element according to the present invention. 1...n+ substrate, 2...n type M (base), 7...conducting path, 3...gate region, 4... ...Emitter area, 5......n
+ type area, 6...Insulator area, 1...
Input terminal, 0t, 02, 0, ... Output terminal, B
...Bias terminal.

Claims (1)

Claims: 1. In a semiconductor body having one conductivity type serving as a base region of a lateral transistor, the other conductivity type serving as an emitter region and a collector region of said lateral transistor spaced apart from each other. forming at least two regions in the collector region of the lateral transistor, which reach into the semiconductor substrate from the surface of the collector region of at least one of the lateral transistors and whose periphery is the collector region of the lateral transistor; A first region made of an insulator in a region close to the surface of the region, and a conductive path of one conductivity type surrounded by a collector region of the lateral transistor below the first region; A semiconductor device comprising a switching element whose gate region is a collector region of a lateral transistor, wherein at least a portion of a conductive path of the switching element is filled with a depletion layer due to a diffusion potential of the gate region. 2. A current source connected to the emitter region of the lateral transistor structure, an input signal source connected to the collector region of the transistor structure, and a current source connected to one end of the conductive path of the switching element different from the base region of the transistor structure. 2. The semiconductor device according to claim 1, further comprising an output terminal.