JPS5910637B2 - Time division multiplex network control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a time division multiplexing network.

Conventionally, in a time division multiplexing network such as a time division switch, in order to easily interconnect a large number of subscribers using a small number of time division communication channels, several channels are set up and pulse trains of corresponding phases are transmitted to each channel. In order to allocate channels to senders and receivers, the addresses of senders and receivers are stored in a circular storage device.

However, in such a conventional system, the reading pulse of the cyclic storage device and the sampling pulse are separate, and the mechanism becomes complicated in order to synchronize them.

The present invention has been made to solve these conventional problems, and controls a time division multiplexing network by using the read pulse of a cyclic storage device as a sampling pulse as a PAM sampling pulse of a corresponding address. The mechanism has been significantly simplified. An embodiment in which the system of the present invention is applied to a time division multiplexing system will be described below with reference to the drawings.

In FIG. 1, memory circuits (RAN-T) 1 and (R
AM-R)2 are readable and writable I
The RAM-Ti stores address data on the transmitting side, and the RAM-R2 stores address data on the receiving side. Also clock counter (CK, COUN)
T) 3 is a register that counts clock pulses, and each time it counts, it specifies the address to be read into RAM-Ti and RAM-R2 using a BCD code.
i or when the data read from RAM-R2 as in the illustrated embodiment is reset data, it is reset and the count is repeated again.

The clock CKG4 provides a clock pulse to CK and COUNT3, and also performs decoding control of the output decoders (described later) of the RAM-Ti and RAM-R2. Tri-state buffer T that does not interfere with each other
SB-i1 and TSB-26 are RAM-Ti and PA
When writing address data to M-R2, write address (
It has a function to replace Da) with the read address by CK and C0UNT3. Reset circuit RFSETDE
When the output data of RAM-Ti or RAM-R2 as in the illustrated embodiment is reset data, CT detects this and resets CK and C0UNT3. Decoder (TODEC) 8 and (RODEC
) 9 decodes the output data of RAM-T1 and RAM-R2, respectively, and provides sampling synchronization pulses for transmission and reception to the PAM time division multiplex network, respectively. The control unit (CONTROL) 10 is an external RAM.
- A signal requesting writing or rewriting of T1 and RAM-R2, that is, a TS specifying RAM-T1, . R.A.
RAM-11, RAM-R2, TSB-15 by the MW signal requesting RSl write specifying M-R2.
and TSB-26 each time, and at the same time control C
K. It has a function to reset COUNT3. That is, CONTROLIO opens TSB-15 and opens TSB-26 unless a signal is given to RS or TS.
, and put RAM-T1 and RAM-R2 into read mode.

Also, when a signal is given to RS or TS, T
When SB-15 is closed and TSB-26 is opened, and a write signal is given to MW, RAM-R2 is written when a signal is given to RS, and RAM-R2 is written when a signal is given to TS. Each RAM-T1 is switched to the write mode and the address data given by Ad is written into the address designated by Da at that time. In addition, TS or R
While the signal is given to CK. Resets COUNT3. Note that the PAM modem unit MDMlla-
MDMnlln are TODEC8 and RODEC9, respectively.
A PAM pulse signal is sent to the time division multipath 12 by the output of the PAM pulse signal, and is received by the time division multipath 12.

Next, in the above device, MDMl (address 1)
The operation of sending a signal from (MDM2 (address 2) to MDM2 (address 2), from MDM2 (address 2) to MDMl (address 1), and from MDM3 (address 3) to MDM4 (address 4) will be explained.

In this case, as shown below, first, (0001) is placed at address O of RAM-T1, and (0010) is placed at address O of RAM-R2.
) is written, and then (00
10), at address 1 of RAM-R2 (0001), RAM
- (0011) is written to the 2nd address of T1, (0100) is written to the 2nd address of RAM-R, and finally the RAM-R
Reset data (1111) is written to address 2-3. For writing, do you write to RAM-T1?
- Specify whether to write to R2 using TS or RS, set the above address to Da, set the data to Ad, and M
This is done by applying a write signal to W.

After writing or rewriting the predetermined address data in RAM-T1 and RAM-R2 in this way, TS and R
If you remove the S signal, it becomes CK. The written address data is finally read out by COUNT3, the data is decoded by TODEC8 and RODEC9, and
PA corresponding to the address data among DMl-MDMn
Give a sampling synchronization pulse to the M modem/demodulator. The operating state at this time is shown in FIG.

That is, when writing is completed and there is no signal on TS and RS, RAM-T1 and RAM-R2 enter the read mode, TSB-15 is opened, TSB-26 is closed, and at the same time, CK. CO-UNT3 changes from the reset state to the count state and starts counting the clock pulses of CKG4 from 0.

So C.K. When the output of COUNT3 was (0000), (0001) and (0010) stored at address O of RAM-T1 and RAM-R2 were read respectively, and TODEC8 and RODEC9 read MDMlla.
The transmission gate of MDM1 is opened to send out the PAM pulse signal to the time division multiplex path 12, and at the same time the reception gate of MDM2 is opened to take in the PAM pulse signal sent out by MDM1.
That is, one sample value is transmitted from MDM1 to MDM2. In this way, CK. When the count of COUNT3 advances and the output becomes (0001), RAM-T1
and stored at address 1 of RAM-R2 (0010
), (0001) are read and this time, MDM2 to M
One sample value is sent to DMl. Thus R.A.
The set data (1) stored at address 3 of M-R2
111) is read, RESETDEC7 detects this and reads CK. Reset COUNT3. After that, CK. COUNT3 starts counting from O again,
Repeat this action. In this way, a new RAM-
When the contents of T1 and RAM-R2 are written or rewritten, MDM1-MDMn (7) controls the PAM modulation/demodulation section and configures the network.

The operating state at this time is shown in FIG. If rewriting is performed, the set data will be written at the end of the valid data. Here, the memory size m of RAM-T1 and RAM-R2 is the total number of channels in the network of this system (however, one channel in one direction).

Also, in the above example, the address data is expressed in 4 bits per word, but in general, if the number of PAM modulation/demodulation units is n, then from the formula 'n=2n, only d bits are required. .

That is, in this case CK. The configuration of COUNT3 may be made to be a minimum m-adic counter, and the word length of address l of RAM-T1 and RAM-R2 may be set as an ibit. Here, the configuration of TSB-15 and TSB-26 is as follows:
It is sufficient to prepare m/bit so that m=2m.

Also, RESETDECr is configured for ibits, and T
The capacitance of ODEC8 and RODEC9 may also be configured to have d bits and n out. Therefore, Da. ．． Ad also,
It is necessary to provide m' bits and ibits, respectively. Here, the clock frequency Fck required for CKG4 is:
It is expressed as Fck=2fs-m.

m is the maximum number of channels, Fs is the highest frequency of the transmission band, and 2 is the transmission number according to the sampling theorem. Furthermore, if the number of channels that guarantee demodulation of Fs is Mch, then Fck = 2fs''Mch, and as the number of used channels increases, the sampling frequency given to one PAM modulation/demodulation section decreases. , Mch, Fs is no longer guaranteed.

For example, if the number of PAM modulators is 16, the maximum number of channels is 8, the number of effective channels is 4, and the transmission band is 8KH2, then CK. COUNT... Octal counter TSB-1, . TSB-2...3-bit RAM-T,
．． RAM-R...8x4 bit RESETDEC...
・4-bit TODEC, . RODEC...4 bits,
16 outs.

Also, the Fck required at this time is Fck=2×8(KH2)×4 264 (KH?.) Therefore, it would be better to set it to 64KH2.

Next, regarding external writing and rewriting control, that is, control of Da, Ad, TS, RS, and MW, there is no problem in fact since the sending of sampling synchronization pulses to the PAM modulation/demodulation section is stopped during this period. It is necessary to process this within a reasonable amount of time.

Considering this point, Da, Ad, TS, RS and MW
The control may be performed manually, but in the case of this method, means using a processor and a computer are effective. In case the transmission signal to be handled is voice, we conducted a separate experiment and assumed rewriting every 1 sec. 12.
Results have been obtained that the time up to about 5m8ec can be virtually ignored. As is clear from the above description, according to the method of the present invention, a network can be easily configured by writing, rewriting, and erasing the network configuration in memory. In other words, it is possible to control the memory as if it were the network itself. Furthermore, the synchronization of the sampling pulses for transmission and reception is achieved by making memory addresses correspond to each other, and the synchronization process can be performed using software. Furthermore, when the number of used channels is small, the quality of the service is high, and as the traffic demand increases, the quality can be lowered to efficiently determine the sampling pulse, and no dedicated IC is used. It can be constructed economically and compactly by using only existing ICs.

In the above explanation, the present invention has been explained with reference to an example in which the present invention is applied to a time division multiplexing PAM conversion system, but the present invention should not be limited to such an embodiment, and can be applied to PCM, . PWM
It can also be used for time division multiplex control, graphic display control such as mosaic display boards, character display control, etc.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the time division multiplex network control method according to the present invention, Fig. 2 is an explanatory diagram showing the operation of each signal in writing, and Fig. 3 shows the operation of each signal in reading. It is an explanatory diagram. 1, 2... Memory device, 3... Clock counter 1, 4... Clock, 5, 6...
... Tristate buffer, 7... Reset circuit, 8, 9... Decoder, 11a to 11n...
...PAM modulation/demodulation circuit.

Claims (1)

[Claims] 1 The storage device is divided into two, and the address data on the receiving side and the address data on the sending side are sequentially stored in the storage devices of different sections, and the address data on the receiving side and the address data on the sending side are Each of the sections is sequentially reproduced at a predetermined time, and the reproduced address data is sent as a sampling pulse to a modulation/demodulation circuit of an address corresponding to the reproduced address data in accordance with the reproduced time. Features a time division multiplex network control method.