JPS5911235B2 - Time-sharing replacement method for load division duplex operation type - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division switching system of load division duplex operation type.

15 shows an example of the method of the switching control section of a conventional time division switch of the load division duplex operation type.

In Figure 1, U' is a line signal conversion circuit that mutually exchanges communication level signals and logic level signals, MPX is a convergence circuit that converges the line 20 received signals coming through the line signal conversion circuit LV, and DMPX is a line signal conversion circuit that performs switching processing. an expansion circuit for sending a line sending signal to the line through the line signal conversion circuit LV; A is a switching processing circuit; 50;
Reference numeral 51 denotes a switching control section CL including the focusing circuit MPX, the expansion circuit DMPX, and the switching processing circuit 25 A.
K is a clock generation source. As shown in the figure, in the conventional time division switching system of this type, the line passes through the line signal conversion circuit LV to the switching controller s.

, S4 both focusing circuits MPX and 30 and expanding circuits DMP
Connected to X. Focusing circuit ■■, expansion circuit DMPX
, the switching processing circuit A is a switching control section s. ,
Both Si types have the same circuit. In other words, it is aggravated. The lock generation source CLK is also duplicated (35). In a time division switching system with such a configuration, when connecting one line to another line, first the line received signal, which is a 01 communication level signal, is converted into a logic level signal by the line signal conversion circuit LV of that line. converted into a switching control unit S.

, Sl. The switching control unit S handles connection processing between lines. , Sl, the switching control unit that is instructed to process at that time (here, S
. on the side). That is, the logic level signal is sent to the switching control section S. The signal is converged by the concentrating circuit MPX, passes through the switching processing circuit A, and is accessed through the expansion circuit DMPX to the line signal conversion circuit LV of the called side line.
The arrow in FIG. 1 shows the direction of connection beyond L. Conventionally, in such a connection method, the entire system had to be operated synchronously, and the switching of signals between the series of lines described above was performed within one time slot (the time allotted for switching processing of one communication). Therefore, the faster the communication speed of the line accommodated in the exchange, the faster the sampling period, and therefore the time of one time slot becomes shorter.
There is a problem in that the processing time for focusing and expansion occupies a large portion within one time slot, and the time for switching processing is compressed and reduced. In addition, a delay time may occur depending on the elements, pattern length, and wiring length used in the converging circuit MPX and expanded circuit DMPX, or the wiring length and pattern length between the converging circuit MPXl expanded circuit DMPX and the switching processing circuit A. was subject to major restrictions. For example, when the speed became high, bus cables could not be used between the focusing circuit MPX, the expanding circuit DMPX, and the switching processing circuit A.
Furthermore, a switching control section S. , Sl, when the clock generation source CLK that supplies both CLK and S1 fails, the backup (clock generation sources are generally duplicated) clock generation source C
There was a drawback that a temporary system shutdown occurred when switching to LK. In order to further increase the number of units, switch the concentrating circuit MPX and expansion circuit DMPX to the switching control circuit S.
, l, and it is necessary to prepare a mounting space in advance for mounting the converging circuit MPX and the expanding circuit DMPX, taking into consideration the pattern length and wiring length described above, which may cause mounting difficulties and waste. was occurring. In Fig. 1, the converging circuit MPX and the expanding circuit DMPX are shown as converging and expanding in two stages, but in reality, as is well known, the converging and expanding circuits of a certain unit (for example, 16-1 data selector (elements) are combined in a tree shape over several stages. The present invention solves these drawbacks by:
The switching control section is separated into a focusing circuit MPX, a developing circuit DMPX, and a switching control section mainly consisting of a switching processing circuit, each of which operates independently and asynchronously, and will be described in detail below.

FIG. 2 is a block diagram of an embodiment of the present invention.

In the figure, LV is a line signal conversion circuit, LGO to LGr
n/n-, a focusing circuit, DMPX is a focusing circuit, CLK is a clock oscillation circuit which is a clock generation source,
CNT is a line number creation counter, RVO,l is a receiver circuit, DVO,l is a driver circuit, LGCHK is an error check circuit, 0R is an OR circuit, NHO,, is a data input bit information line, SWO,l is a switching processing unit, L.I.
MC is a line interface memory control unit, LIM is a line interface memory, LCTL is a line interface memory control circuit, SCTL is a switching processing circuit, ?
M is a switching memory, SD is line sending data (signal), and RD is line receiving data (signal). Also the third
The figure shows an example of the configuration of the line interface memory LIM. In FIG. 3, SDM is a line sending data SD storage memory, RDM is a line receiving data RD' storage memory, and SD
MAD is the address of the SDM, RDMAD is the address of the RD
M's address, LNO-. -1~. 1 indicates the line number. FIG. 4 is an example of a time chart of the operation of the present embodiment, and the present embodiment will be described below with reference to FIGS. 3 and 4 as well. Note that in the figure, there are several symbols as numbers, such as 0 to n-1, but since they are numbered starting from number O, this indicates that in the case of n numbers, the last number will be n-1. The same applies to 0 to m-1, 0 to l-1, etc. 6 As shown in Fig. 2, the configuration of this embodiment is such that the part corresponding to the conventional switching control section S is expanded into a convergent circuit MPX as a device unit. The circuit is divided into a focusing/deploying section LG which handles focusing/deploying functions mainly based on the circuit DMPX, and a switching processing section 8V which performs switching processing, and the line is connected to a line signal conversion circuit L.
Through V, the total lines (m lines in the example of FIG. 2) are divided and accommodated in each focusing/deploying unit LG.

(In the example shown in Fig. 2, each focusing/deploying unit LG accommodates n lines,
Therefore, there are m/n focusing/expanding sections LG.) Of course, all the focusing/expanding sections LGO-m/n-1 are the same circuit, and both the switching processing sections SWO,l are the same circuit.

The focusing circuit MPX and the developing circuit D are in the focusing and developing section LG.
In addition to MPX, a clock oscillation circuit CLK is arranged for each focusing/deploying section LG, and separate switching processing sections SWO,
A receiver RVO,l and a driver DVO,l are provided to access both. Note that two switching processing units 8V are generally sufficient. On the other hand, in addition to the switching processing circuit SCTL, the switching processing unit 8V also includes a line interface memory control unit LIMC that stores data sent to each line and data received from each line, corresponding to each focusing/deploying unit LG. A number of focusing circuits M are provided corresponding to the number of expansion units LG and converge the data from the control unit LIMC.
PX and a switching memory for storing switching control data are provided. The switching memory?
The switching control data for M is stored in the switching memory of one of the switching processing units SWO, . . . in the case of the time division switching method of the load division redundant operation type, as is well known. Stored in y. That is, when the data stored in the switching memories of both switching processing units SWO and SWO are combined, all switching control data is stored. Although not shown, this switching processing unit SWO,l is also naturally provided with a clock oscillation circuit. With the above configuration, it is not necessary to double the focusing/deploying section LG as in the conventional case, and a single one is sufficient. Also, line transmission/reception data SD, S
By storing D in the line interface memory control unit LIMC of the switching processing unit 8V, each focusing/deploying unit LGO~n]/n-, and the switching processing unit SWO,l can operate independently and asynchronously. , it is not necessary to perform a series of switching processes for connecting lines to each other within one time slot as in the past, and therefore the focusing/deploying unit L
There is no need to speed up the sampling period of G so much.
It becomes possible to connect a bus cable between the focusing/deploying section LG and the switching processing section SW. In this example, the total number of lines is m lines, and the number of lines accommodated in one focusing/deploying section LG is n lines, so the number of focusing/deploying circuits LG is m/n. If the number of possible lines is l (address O-1-1 of the switching memory circuit corresponds to this) and the line signal sampling leap period is T, then the switching processing unit? The allocation processing time per communication within v is T/l
, the line signal sampling period in the focusing and expanding section LG is T/n (T/n>T/l). The connection operation of this embodiment configured as above will be explained below. The line is accommodated through the line signal conversion circuit L to the focusing circuit and expansion circuit DMPX of the focusing and expansion unit LG.

The line signal conversion circuit L converts the communication level signal from the line into a logic level signal, and the convergence and expansion of the signal is performed by the clock oscillation circuit CLK in the convergence and expansion unit LG for the LG created by the line number creation counter CNT. Line number (0
~n-1) as the address. A line reception monitor RD of a plurality of converted logic level signals is condensed and developed by a unit L.
The signal is focused by the focusing circuit MPX of G, and simultaneously transferred to the switching control section 81 through the driver DVO and to the switching processing section SW through the driver DVl. At this time, the LG line number is also transferred. In the time chart of Fig. 4, LGLNO of LG(x) indicates the line number for LG created by the line number creation counter CNT and T/n.
The next line number is sequentially specified on a cycle-by-cycle basis. Then, as described above, the data is focused by the focusing circuit MPX, and the line reception data RD of the designated line is extracted as shown by RD in the chart of FIG. (for example, RDO) and sends the RD and the line number LGLNO to a line sending data request signal (SD
along with the request signal) REQ, the switching processing unit SWO,
, transfer to. The REQ portion of SWO,l in FIG. 4 indicates the timing of the transfer. Switching processing unit SWO
The line reception data RD transferred to the line interface memory control unit LIMC passes through the receiver RV of the line interface memory control unit LIMC, and is received at the access timing for the focusing and expansion unit (hereinafter referred to as the access timing for LG) under the control of the line interface memory control circuit LCTL. , the LG line number LGLNO sent from the convergence expansion unit LG is stored in the line reception data storage memory RDM shown in FIG. 3 in the line interface memory LIM which is accessed as an address. In parallel with this, the line interface memory control unit LI
The MC uses the LG line number LGLNO as an address to read out the line sending data SD stored in the manner described later from the line sending data storage memory SDM shown in FIG. 3 in the line interface memory LIM at the LG access timing. . (Chart SD part in Figure 4) In the timing chart in Figure 4, the SD of LG(x)
The manner in which the request signal REQ is received by the switching processing unit SWO,l is shown in the REQ chart of SWO, , in the figure. LGLNO=0 and RD at the first REQ signal
It is also illustrated that O is transferred together. The line reception data RD and line transmission data SD are stored in the line reception data storage memory RDM and line transmission data storage memory SDM arranged as shown in FIG. 3 in the line interface memory LIM as shown in the figure. An address SDMADO corresponding to the number of lines (n in this example) accommodated in the corresponding focusing/deploying unit LG is stored in a memory provided with one word for each line.
−. One, TsuRDMADO-. 1, and stored in the memory indicated by line numbers LNO=O-n-1 to m-n-1 to n-1 for each line. This memory SDM,
Control of read/write of the RDM is performed by the line interface memory control circuit LCTL as described above. Switching memory? The number of lines that can be communicated at the same time is 1.
Switching control data is stored in one word corresponding to a line. And this switching control data has a period T
The switching processing circuit SCT
Read to L.

That is, the processing time for one piece is T/1. Then, using the line number in the switching control data, the line reception data RDO- is sent from the line reception data storage memory RDM of each line interface memory control unit LIMCO-m/n-1 using, for example, the lower pit of the line number as an address.
Read Rn/n-1. Next, the line received data R
DO, nl/n-1 is, for example, a focusing circuit MPX (switching control unit output Vf) MPX with the upper bit as the address.
) to focus. In other words, the line data RD from each focusing/deploying unit LGO-m/n-1 is transferred and stored in each line interface memory control unit LIMC of the switching processing unit 8V. It converges. The timing chart for writing and reading line reception data RD and line transmission data SD is shown in the chart of Rm data, RDMAD, and SDMAD in FIG. 4. In this chart, the shaded area
. , l..., YO, death... are timings used during switching control, and the non-hatched portions are the aforementioned LG access timings. That is, under the condition that the line reception data RD is transferred from the focusing/deploying unit LG, read/write is performed as shown by numbers 0 and 1 in FIG. 4 at the LG access timing immediately after that. . Switching memory again? The timing chart for reading the line number from the notebook is SWM in Figure 4.
It is shown in the chart of AD and LNO. When the address output UD of the switching memory unit is a1, set the line number LNO to X. is read out and the line reception data memory RDM (fourth
In the figure, from RDMAD) to the X. This example shows that the line reception data RD specified by is read out. (b
1-YO), the line reception data RD focused as described above is subjected to switching processing according to the switching control data read out by the switching processing circuit SCTL, and as a result, line transmission data SD is created. .
The created line sending data SD is stored in a location corresponding to the line number of the line sending data storage memory SDM of any one of the line interface memory control units LIMCO-m/n-1.

The line sending data SD read out at the aforementioned LG access timing is read out from the SD stored as described above. The timing is illustrated in the SD chart part of SWO, 1 in FIG. Line sending data S
When the reading of D is completed, the line sending data SD and response signal ASW are sent back to the focusing and expanding unit LG through the driver DV of the line interface memory control unit LIMC.

The focusing section LG receives this returned line sending data SD through the receiver R, and sends it to the error check circuit LG.
An error check is performed at CHK, the signal is expanded by an expansion circuit DMPX through an OR circuit 0R, and the signal is converted into a communication level signal by a line signal conversion circuit LV and sent to the line specified by the LG line number LGLNO. Note that the data inhibit information lines 1NH0 and 1NH0, 1 connected to the OR circuit 0R are used to inhibit the line sending data SD and control data, and are used in the event of a failure. Furthermore, in the timing chart of FIG. 4, SDSET, which did not appear in the above explanation, is the timing for sending out the line sending data SD, and RDMWE is the timing for writing the line received data RD into the line received data storage memory RDM. . As explained above, the switching processing unit SWO1 has the focusing/deploying unit LGO~n1.
Since the line interface memory control unit LIMCO-m/n-1 corresponding to each of The LGO-m/n-1 and the switching processing unit SWO,l can each independently send and receive information in parallel, and each can operate asynchronously.

Therefore, according to this embodiment, since each focusing section LG and each switching processing section output M have a clock oscillator circuit CLK, even if the clock system involved in switching control is disconnected, the switching will cause a temporary There is no system down.

Furthermore, since the focusing/deploying section 8M and the switching control section 8M can each be operated independently as described above, compared to the conventional method in which focusing/deploying and switching control processing are performed within one time slot, this is divided. The sampling period of the focusing/deploying section LG will have some leeway, and the switching processing section? The V switching processing time can be increased compared to the conventional method. In other words, is the sampling period of the focusing/deploying unit LG the switching control unit? This is 1/n times the sampling period of . In other words, there is no need to increase the speed so much, and the connection between the focusing section LG and the switching processing section output v can be sufficiently handled using a bus cable or the like. This in turn makes it possible to make the focusing/deploying unit LG into one expansion unit,
This is very effective in terms of installation. Focusing development part LG
Since it is single-layered, the total cost of installation can be made more economical. As described above, according to the present invention, in the time-sharing switching system of the load division redundant operation type, it is possible to eliminate temporary system downtime due to clock system failure, and to realize an economical time-sharing switching system that is extremely easy to expand. be able to.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a switching control section of a conventional load division duplex operation type time division switching system, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a circuit interface memory shown in Fig. 2. FIG. 4 is a timing chart of the embodiment.

Claims (1)

[Claims] 1 In the time-sharing switching system of load division redundant operation type,
The switching control unit is a device unit, and the switching control unit includes a convergence and expansion unit that accommodates a certain number of lines and has the functions of transmitting the line and concentrating and expanding received data, and a switching processing unit that has the main switching processing function. The convergence/deployment section has a function of concentrating at least the received data of the line accommodated and transmitting it simultaneously to a plurality of the switching processing sections, and a function of transmitting line transmission data returned from the switching processing section. The switching processing section has a function of receiving, decompressing and transmitting the data to the line, and a clock oscillation circuit necessary to control these functions, and the switching processing section receives and processes at least the line reception data transferred from the convergence and decompression section. The line interface memory control unit, which is composed of a memory for storing data, a memory for storing line transmission data created by switching processing, and a control circuit for controlling storage to and reading from these memories and transfer of the read data, is concentrated and expanded as described above. a function of connecting with a corresponding convergence/deployment section, a function of concentrating the line reception data read from the memory control section and performing switching processing, and a function of transferring the line transmission data to a predetermined memory control section; A time sharing load division duplex operation type characterized in that it has a switching memory that stores necessary switching control data, and that each of the focusing/deploying section and the switching processing section enables asynchronous operation for each device. Exchange method.