JPS5911294B2 - FM stereo signal separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to an FM stereo receiver, and particularly to an FM stereo receiver.
The present invention relates to an M stereo signal separation circuit.

As is well known, FM stereo receivers that receive FM stereo broadcasts in which both left and right channel signals are combined and transmitted are capable of combining (composite) FM stereo signals.
An FM stereo signal separation circuit is required to separate the signals.

FIG. 1 shows such an FM stereo signal separation circuit based on a conventionally known switching system.

That is, the input signal from the composite signal source e1 is input as an FM stereo signal supplied via the preamplifier A1 consisting of transistors Ql and Q2 to the lower stage difference in the double-balanced differential amplifier DBA consisting of transistors Q3 to Q8. 7) at one input end of the moving part.
By switching it with the switching signal from the 38KH7 switching signal source e2 applied to both input terminals of the upper differential section of the double-balanced differential amplifier DBA, both output terminals of the upper differential section Lou ，
The left and right channel signals are separated and derived from Rout.

In the figure, Q9 sQto is a bias circuit transistor for applying a predetermined bias voltage to the other input terminal in the lower differential section of the double-balanced differential amplifier DBA.

By the way, in such a conventional switching type FM stereo signal separation circuit, distortion is reduced by applying a negative feedback loop in the preamplifier A1 section, but the double-balanced differential amplifier DBA The distortion of the switching circuit itself will not be reduced and will remain as it is. However, it had the disadvantage of poor distortion characteristics.

Therefore, the present invention has been made in view of the above points, and provides an extremely good FM that can easily and reliably reduce the distortion of the switching circuit itself and is particularly suitable for integrated circuits.
The purpose is to provide a stereo signal separation circuit.

That is, the FM stereo signal separation circuit according to the present invention includes first and second transistors whose respective bases are connected correspondingly to an FM stereo signal source to be separated or a bias voltage source, and these first and second transistors. The bases are connected correspondingly to the collectors of the third and fourth transistors forming the lower differential section, and
The common emitters are connected correspondingly to the respective collectors of the transistors, and the fifth and sixth transistors constituting the upper differential section
and a seventh and eighth transistor, and a 38KHz switching signal source is connected between the common bases of the sixth and seventh transistors and between the common bases of the fifth and eighth transistors. In a switching type FM stereo signal separation circuit using a double-balance type differential amplifier configured to be able to derive left and right channel separated signals correspondingly from the respective common collectors of the sixth and eighth transistors, the seven-stage differential section is The fifth, sixth and seventh constituent parts
, each base is correspondingly connected to each base of the eighth transistor, and each common emitter is correspondingly connected to each common emitter of the fifth, sixth, seventh, and eighth transistors. The ninth, tenth, eleventh, and twelfth transistors are energized, and the common collectors of the ninth, tenth, eleventh, and twelfth transistors are connected to the respective emitters of the first and second transistors. It is characterized by a corresponding return connection.

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, as shown in FIG. 2, the input terminal IN1 is connected to the composite signal source e1 as an FM stereo signal.
is connected via a capacitor C1 to the base of a transistor Q,t forming a preamplifier A11.

The emitter of this transistor Qll is the resistor R1.
It is connected to the power supply Vcc via a common collector of transistors Q14 t and Q15, which will be described later, and the collector is connected to the base of a transistor Q1, which will be described later.

? Here, the transistors Q1, Q14, and Q15 are transistors Q1s t Qta to Q2, which will be described later.

Together, they constitute a double-balanced differential amplifier DBA1.

Of these, the transistor Q constituting the lower differential section
The emitter of transistor 1 is directly grounded, and the collector is connected to the common emitter of transistors Q, 3 to Q, 6.

Similarly, the emitter of the transistor Q1 constituting the lower differential section is directly grounded, and the collector is connected to the transistor Q1.
Connected to the common emitter of 8 to Q21.

Further, a 38 KHz switching signal source e2 is connected between the common bases of the four transistors Q13, Q14 and Q2o, .

Furthermore, the transistor Q+3 is arranged in a cross-layered manner.
+ Qts and the common collectors of the transistors QI6 t Q20 are connected to the power supply Vcc via corresponding resistors R2 and R3, respectively.

Further, the common collectors of the transistors Q19 and Q20 are connected to the power supply VCC via the resistor R4 and to the emitter of a bias circuit transistor Q2, which will be described later.

The collector of this bias circuit transistor Q22 is connected to the base of the transistor Q17, and the base is connected to the power source vB through the resistor R5.

Further, this power supply vB is connected to the base of the transistor Qtt via a resistor R6.

Note that in the above, the common collectors of the transistor Q13 t Qts and the transistors Q1a + Q21 are respectively connected to the output terminal LouttRout.

} Therefore, in the above configuration, when the 38K}I2 switching signal source e2 receives the 38KH7 switching signal in the positive half cycle period, the 38KH7 input signal forms the upper differential section of the double-balanced differential amplifier DBA11. transistors Q13, Q14 and the other transistor. Transistors Q20 and Q21 are in the on state, and one of the transistors Q15 and Q+a and the other transistor (h.st QI9) are in the off state.

Therefore, at this time, the load resistor R2 is connected to the transistor Q. 3
The left channel signal current flows through the output terminal L
The left channel output signal is separately derived from out.

Further, at this time, the signal current is returned to the emitter of the transistor Q11 via the transistor Q14, and the bias current is returned to the emitter of the transistor Q2? via the transistor Q20. He has been returned to Emitsuta.

On the other hand, when the 38KHz switching signal is in the negative half cycle period, contrary to the above, transistor Q15
, Q16 and transistors Qta, Q19 are on, and transistor Q13414 and transistors Q2, Q21 are off.

Therefore, at this time, the transistor Q. The signal current of the right channel flows through the output terminal Rout
The right channel output signal is separately derived from .

Also, at this time, the signal current is returned to the emitter of the transistor QQll via the transistor Q15, and
The bias current is returned to the emitter of transistor Q2 via transistor Q19.

In other words, as described above, the signal current is always connected to the preamplifier A regardless of the positive or negative period of the 38KHz switching signal.
1, and the bias current is returned to the transistor Q11 forming the bias circuit.
It will be returned to 2.

In this case, the double-balanced differential amplifier DBA,
, transistors Q12 to Q for switching circuits consisting of
21 with the same characteristics as possible, and the load resistance R1
If R4 is selected to have the same resistance value, the collector-emitter voltages VCE of the transistors Q12 to Q21 will have the same value.

Therefore, the switching distortion at this time is the transistor Q
1a and Q+41 transistors Q15 and Q+a, transistors Q+8 and Q+9 and transistors Q20 and Q2
, and since it equivalently occurs within the negative recursion loop, it is possible to reduce it to a sufficiently small value due to the effect of the negative recursion ring.

Furthermore, in this case, it goes without saying that the distortion generated within the negative feedback loop is reduced.

In the above description, it is assumed that the emitter currents of the transistors Q11 and Q22 take values sufficiently smaller than the respective collector currents of the transistors Q+2 to Q21.

The FM stereo signal separation circuit as described above has a simple configuration and can reliably reduce distortion of the switching circuit section itself, and is particularly suitable for integration into an integrated circuit.
The transistors Q 1 2 -
This is convenient because it is easy to make the characteristics of Q2t the same and the resistance values of the load resistors R1 to R4 the same.

It goes without saying that the FIFM stereo signal separation circuit described above can be modified in various ways, not only in the embodiments described above, but without departing from the gist of the present invention.

Therefore, as detailed above, according to the present invention, it is possible to easily and reliably reduce the distortion of the switching circuit section itself, and to provide an extremely good FM stereo signal separation circuit particularly suitable for integration into an integrated circuit. can.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram showing a conventional FM stereo signal separation circuit, and FIG. 2 is a wiring diagram showing an embodiment of the FM stereo signal separation circuit according to the present invention. e1...FM stereo (composite) signal source, e
2...38KHz switching signal source, A,i...preamplifier, DBA...double balanced differential amplifier (
switching circuit section), Q, . ~Q2+...transistor, Q22...bias circuit transistor, vo
c, vB...Power supply, R1 to R4...Load resistance, R
5, R6... (bias input) resistance, C1... (
coupling) capacitor.

Claims (1)

[Claims] 1 First and second transistors, each base of which is connected correspondingly to an FM stereo signal source or bias voltage source to be separated, and each base is connected correspondingly to each collector of these first and second transistors. The third and fourth transistors constituting the lower differential section, and the respective common emitters are connected correspondingly to the respective collectors of these third and fourth transistors, and the upper differential section a 38 KHz switching signal source is connected between common bases of the sixth, seventh, fifth, and eighth transistors constituting the In a switching type FM stereo signal separation circuit using a double-balance type differential amplifier configured to be able to derive left and right channel separated signals correspondingly from the common collectors of the fifth, seventh, sixth, and eighth transistors, Each hese is connected correspondingly to the bases of the fifth, sixth, seventh, and eighth transistors constituting the upper differential section, and Ninth, tenth, eleventh, and twelfth transistors are added to each common emitter, and each common emitter is connected correspondingly to the ninth, tenth, and eleventh transistor.
, the common collectors of the twelfth transistors are connected to the common collectors of the first and twelfth transistors.
An FM stereo signal separation circuit characterized in that the circuit is connected in a loop to each emitter of a second transistor.