JPS5846898B2 - stereo fukuchiyou warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo demodulation circuit having a muting function.

The muting circuit of a conventional FM radio receiver has a switching means inserted in the signal path and is controlled by a muting control signal, which has the disadvantage of generating a large amount of noise when transitioning to and exiting muting. there were.

In view of the above, it is an object of the present invention to provide a stereo demodulation circuit having a muting function that generates less noise during muting transition and exit.

Hereinafter, one embodiment of the present invention will be explained in detail with reference to FIG.

In Figure 1, 1 is an input terminal to which a composite stereo signal is supplied, 2a and 2b are input terminals to which a 38 kHz subcarrier signal is supplied, and 3L and 3R are left and right audio signal outputs which are stereo demodulation outputs. It is a terminal.

Further, 4 is a power supply terminal, to which a power supply element B is connected.

6 and 1 are first and second differential amplification circuits to which composite stereo signals are respectively supplied.

10 consists of third and fourth differential amplification circuits 8 and 9;
This is a multiplication circuit to which the subcarrier signal and the composite stereo signal from the first differential amplification circuit 6 are supplied and multiplied.

23 is a current relay circuit (current mirror circuit).

Reference numeral 34 denotes a transistor serving as a muting control means for reducing the constant current flowing through each constant current transistor Q3-Qa of the first and second differential amplifier circuits to approximately zero.

The first differential amplification circuit 6 has amplification transistors QI-Q2.
and a constant current transistor Q3.

The amplification transistor Q1 consists of transistors Q1a and Qlb connected in a Darlington connection, and the other amplification transistor Q2 consists of a transistor Q connected in a Darlington connection.
2a and Q2b.

A bias voltage is applied to the constant current transistor Q3 by a bias current E1.

The emitter of transistor Q3 is grounded through resistor 36.

The second differential amplifier circuit 7 includes an amplifier transistor qQ5 and a constant current transistor Q6.

The amplifier transistor Q4 is composed of Darlington-connected transistors Q4a, Q, and b, and the other amplifier transistor Q is composed of Darlington-connected transistors Q5a and Q5b.

Further, a bias is applied to the constant current transistor Q6 by the bias power source E1 described above.

The emitter of transistor Q6 is grounded through resistor 31.

As described above, the multiplication circuit 10 is composed of the third and fourth differential amplification circuits 8 and 9.

The third differential amplification circuit 8 is composed of amplification transistors Q71% and Ql.

The fourth differential amplifier circuit 9 includes an amplifier transistor Q9 tQ.
It consists of loz and Q2.

A subcarrier signal of 38 kElz is supplied as a balanced input to the third and fourth differential amplifier circuits 8 and 9 from the input terminals 2a and 2b.

This multiplication circuit 10 includes each amplification transistor Ql of the first differential amplification circuit 6.

They are connected so that they are stacked on the collector side of Q2.

The collectors of transistors Q7 and Q are connected to power supply E3 through a load resistor 20, and the collectors of transistors Q7 and R
and Qto are connected to the power supply E through a load resistor 21.
Connected to 3.

These load resistors 20 and 21 have the same resistance value RL.

A left audio signal output terminal 3L is led out from each collector of transistors Q7 and Q9, and a right audio signal output terminal 3R is led out from each collector of transistors Q8 and Qlo.

Current relay circuit (current mirror circuit) 23 is multiplication circuit 1
A pair of transistors Q1□IQI□ and a transistor Q4 of the second differential amplification circuit γ are connected so as to be stacked on the collector side of each transistor of the third and fourth differential amplification circuits 8 and 9 of 0. Transistor Q1 connected to the collector side
It is composed of 3 j Q14.

The collectors of transistors Q7 and Q are connected to the collector of transistor Qll, and the emitter of transistor Q1□ is connected to power supply terminal 4.

Furthermore, the collectors of transistors Q8 and QIO are connected to the collector of transistor Q1□, and
Twelve emitters are connected to the power supply terminal 4.

The collector of the transistor Q4, that is, Q4a is connected to the collector of the transistor Q14 and the base of the transistor Q13, the emitter of the transistor Q14 is connected to the power supply terminal 4, and the collector of the transistor Q13 is grounded.
The emitter of transistor Q13 is connected to the base of transistor Q14, and transistors Qll and Q1
Connected to each base of 2.

In this way, a current based on the composite stereo signal flowing between the collector and emitter of transistor Q14 is relayed to transistors Q1□ and Q12.

A bias power supply (constant voltage power supply) E2 is used for each of the first and second differential amplifier circuits 6 and γ transistors Qt-Q2, Q4, and Q, and a resistor 15 having the same resistance value is connected to each transistor.
, 16, 1γ and 18.

Then, the composite stereo signal from input terminal 1 is connected to resistor 1.
9, the transistor Q2 of the amplifier circuit 6, i.e. %Q2a
and a variable resistor 5 for controlling composite stereo signal casseparation.
The signal is supplied to the base of the transistor Q5, that is, Q5a of the second differential amplifier circuit γ.

The bias power source E1 for the constant current transistor Q3-Qa of the first and second differential amplifier circuits 6, 1 is connected between the power supply terminal 4 and the ground through the resistor 30-resistor 31-
Consists of a series circuit of diode 32 and resistor 33,
A midpoint between the resistor 31 and the diode 32 is commonly connected to the bases of the transistors Q3 and Q6.

In this case, the resistors 33, 36 and 31 have the same resistance value, and the forward voltage drop of the diode 32 is the same as that of the transistor Q3.
．． It is made equal to the base-emitter voltage of Qa.

The collector of a transistor 34 serving as a muting control means is connected to the midpoint between the resistors 30 and 31, and its emitter is grounded.

Further, an input terminal 35 is led out from the base of the transistor 34, and a muting control signal is supplied from there to the base of the transistor 35.

As in the past, a circuit (not shown) is provided that detects the intermediate frequency signal from the FM intermediate frequency amplification circuit (amplitude detection) and provides an output when the detected output is below a predetermined level, and mutes the output. It is used as a timing control signal.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the circuit shown in FIG. 2.

In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals and redundant explanation will be omitted.

In FIG. 2, 21 and 28 indicate current sources for the multiplication outputs -(R-L) and -(LR) from the multiplication circuit 10.

Further, 25 and 26 respectively indicate current sources of the main audio signal R+L in the composite stereo signal from the second differential amplification circuit γ.

Then, the left audio output obtained by adding the currents from the current sources 26 and 28 is obtained at the output terminal 3L, and the output terminal 3R
In this case, the right audio output is obtained by adding the currents from the current sources 25 and 2γ.

The DC level of the stereo demodulated output obtained from the output terminals 3L and 3R is always kept at the same constant value by the voltage of the current E3, and the DC level of the stereo demodulated output obtained from the output terminals 3L and 3R is always kept at the same constant value by the voltage of the current E3. γ
It is not affected by the magnitude of the constant current flowing through the constant current transistor QatQ6.

The gain of a differential amplifier circuit is determined by the product of mutual conductance and load resistance, and the mutual conductance depends on the constant current of the constant current circuit, and the smaller the constant current, the smaller the gain.

Further, the constant current flowing between the collector and emitter of the transistor Qa=Qa depends on the voltage of the power source E1 and is equal to the current flowing through the diode 32.

When the level of the received signal is high enough, transistor 3
4 is off, a predetermined current determined by the voltage of the power supply E1 flows through the constant current transistor Q3=Qe of the first and second differential amplifier circuits 6 and 1, and the second equal amplifier circuit operates normally. death,
Stereo demodulated outputs, that is, left and right audio signals are obtained from the output terminals 3L and 3R.

When the level of the received signal is below a predetermined level, the transistor 34 is turned on, the voltage of the power supply E1 becomes zero, and the constant current transistors Q3 . Q6 is cut off and the current flowing through them becomes zero.

Therefore, the second magnification circuit stops operating, and the output terminal 3L,
You will not be able to get a stereo demodulated output compared to 3R,
Muting is performed.

Furthermore, by adjusting the separation control resistor 5, the input level of the composite stereo signal supplied to the second differential amplification circuit T, especially its main audio signal component, can be varied. Separation control is broken.

In this case, the transistors Q2 and Q of the first and second differential amplifier circuits 6 and 1 are supplied with composite stereo signals, respectively.
Since the base potentials of resistors 19 and 5 are exactly the same,
No direct current flows through the terminals 3L and 3R, so the direct current level of the stereo demodulation output from the stereo demodulation output terminals 3L and 3R does not change.

According to the above-described stereo demodulation circuit of the present invention, the first and second differential amplification circuits, the third and fourth differential amplification circuits, to which composite stereo signals are respectively supplied, and the first and fourth differential amplification circuits are provided. a muting control circuit that reduces the constant current flowing through the constant current circuit of the second differential amplification circuit to approximately zero; The composite stereo signal from the dynamic amplification circuit is supplied and multiplied to demodulate the left and right stereo signals, and the second difference is added to the demodulated signal from the third and fourth differential amplification circuits. The composite stereo signal from the dynamic amplification circuit is added to obtain a stereo demodulated output from which crosstalk components have been removed, and during muting, the first, second and third signals are controlled by the muting control circuit. By setting the current in the constant current circuit of the fourth differential amplification circuit to zero, the gain of each differential amplification circuit is made zero, and the stereo demodulation output is blocked. By supplying DC voltage to the input terminal of the second differential amplification circuit and fixing the output DC level of the third and fourth differential amplification circuits, stereo demodulation is performed during muting transition and exit. Since the DC level of the output does not change, the gain of the amplifier simply changes at the time of muting transition and exit, and the DC level of the stereo demodulation output does not change, so noise generation at that time is reduced. few.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the stereo demodulation circuit of the present invention;
FIG. 2 is a circuit diagram showing such circuits. 6, γ, 8 and 9 are first to fourth differential amplifier circuits, respectively;
10 is a multiplication circuit, 23 is a current relay circuit (current mirror), and 34 is a muting control means.

Claims (1)

[Claims] 1. First and second differential amplification circuits, third and fourth differential amplification circuits to which composite stereo signals are respectively supplied, and constant current of the first and second differential amplification circuits. a muting control circuit that reduces a constant current flowing through the circuit to approximately zero, and a subcarrier signal and a composite stereo signal from the first differential amplification circuit are supplied to the third and fourth differential amplification circuits. The left and right stereo signals are demodulated by being multiplied, and the composite stereo signal from the second differential amplification circuit is added to the demodulated signals from the third and fourth differential amplification circuits. A stereo demodulated output from which the crosstalk components are removed is obtained by addition, and during muting, the 11th second and third
By setting the current in the constant current circuit of the fourth differential amplification circuit to zero, the gain of each differential amplification circuit is made zero, and the stereo demodulation output is blocked, and the first and supplying a DC voltage to the input terminal of the second differential amplification circuit to fix the output DC level of the third and fourth differential amplification circuits at the time of muting transition and escape. A stereo demodulation circuit characterized in that the DC level of the stereo demodulation output does not change.