JPS5912221B2 - vertical synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to synchronization means for a device that divides a signal having a frequency that is an integral multiple of the horizontal frequency to create a signal for vertical deflection.
The aim is to provide a device that can perform accurate synchronization.

In a television receiver, a 5 signal with a frequency nfH, which is an integral multiple of the horizontal frequency fH, is generated in synchronization with a horizontal synchronization signal, and this is frequency-divided in synchronization with a vertical synchronization signal to produce a signal with a vertical frequency fv. It is known to perform vertical deflection using frequency-divided output.

In such a device, the position and magnitude of the vertical synchronization signal Vs extracted from the television signal are likely to change due to signal jitter, drift, etc., but the vertical synchronization signal is differentiated and waveform shaped. Since the operating point of the circuit that creates the reference signal for synchronization tends to change due to temperature changes, the pulse width of the reference signal also changes easily.Furthermore, the 15 circuits that detect the phase shift also have large fluctuations, making it difficult to receive signals. The disadvantage is that the tolerance for fluctuations in the television signal and processing circuit is small, resulting in an unstable deflection state. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a 20 vertical synchronizer that can eliminate such conventional drawbacks and perform stable deflection operation with a large margin. The present invention is characterized in that a signal is stably generated and phase shifts are accurately detected. Hereinafter, the present invention will be described in detail with reference to FIG. 25 showing one embodiment thereof.

Figure 1 shows its configuration, where 1 is an antenna, 2 is a tuner, 3 is a VIF circuit, 4 is a video detection circuit, 5 is a signal processing circuit for amplifying the luminance signal and reproducing the color signal, and 6 is a signal processing circuit for amplifying the luminance signal and reproducing the color signal. A synchronization separation circuit, 7 a horizontal deflection circuit, 8 a vertical deflection circuit, and 9 a cathode ray tube are similar to those of a general television receiver.

10 is a horizontal frequency fH (-, 15.75KH) in synchronization with the horizontal synchronization signal Hs extracted from the television signal.
2fH to create signal 35 with frequency 2fH twice that of 2)
The generation circuit 11 is a frequency dividing circuit that divides this 2f boiling point into 1/525 to generate a vertical deflection pulse VD having a vertical frequency fv (-, 60H2) and a constant pulse width (7.5H width). , 12 is a reference signal generation circuit that generates a reference signal VR with a constant pulse width (7.5H width) in synchronization with the vertical synchronization signal Vs extracted from the television signal, and 13 is a reference signal generation circuit that generates the frequency-divided output VD and the reference signal VR. A phase comparison circuit 14 compares the phases and generates a gate pulse Gp during a period in which the two phases are out of phase.
The number of 2fH signals taken out is counted, and the count value is a predetermined value (here, the count value is 6).
91) A counter circuit 15 generates a reset control signal Rc when the control signal Rc is generated, and a counter circuit 15 resets the frequency dividing circuit 11 when the control signal Rc is generated, and vertically outputs a reset pulse RD to match the phases of the two. This is a set pulse generating circuit which gates and extracts the vertical synchronizing signal Vs only when the resetting control signal Rc is generated in synchronization with the synchronizing signal Vs. However, here,
H has a horizontal period=1/FH. Next, the detailed configuration and operation of these circuits will be explained.

First, the frequency dividing circuit 11 divides the frequency of the generated signal 2fH from the 2fH generating circuit 10 by 1/525 using 10 stages of JK flip-flops 16 to 25 connected in cascade and a NAND gate 26 to obtain a pulse width of 7. At 5H, a divided output VD of vertical frequency f is generated. This frequency-divided output VD is applied to the vertical deflection circuit 8. In turn, this supplies a sawtooth wave current for vertical deflection to the vertical deflection coil. On the other hand, the reference signal generation circuit 12
is a JK flip-flop 27 that counts the 2fH signal.
30, a D-type flip-flop 31 and a NAND gate 32 that synchronize the counting start timing with the vertical synchronizing signal Vs and the 2f bisymbol, and a constant reference signal with a pulse width of 7.5H is created by them. A NAND gate 33 and an R-S flip-flop 34 are constructed as follows.

First, the vertical synchronizing signal Vs is transferred to the flip-flop 31.
By applying an inverted signal of the 2f1 signal to the C terminal of the flip-flop 31 in addition to the D terminal of the flip-flop 31, an output Vs' in which the leading edge of V1 is almost at the same position as the vertical synchronizing signal Vs and synchronized with the 2fH signal is obtained. Then, these 2fH signals, the vertical synchronization signal Vs, and the synchronized vertical synchronization signal V are added to the NAND gate 32, and one pit of the first 2fH signal immediately after the leading edge of the vertical synchronization signal Vs is set as the counter reset signal R.
As a result, the counter consisting of flip-flops 27 to 30 is reset, and the 2fH signal is then counted to obtain a count output. After counting 15 2fH signals, the 2fH signal is gated by the NAND gate 33 to reset the flip-flop. Obtain the set signal RF. Then, the flip-flop 34 is set by the counter reset R from the NAND gate 32, and the flip-flop 34 is reset by the flip-flop preset signal RF from the NAND gate 33, so that the width of one pulse is always constant at 7.5H. A reference signal VR is created. The leading edge position of this reference signal VR is synchronized with the 2fH signal immediately after the leading edge of the vertical synchronizing signal Vs}V1. , here, the pulse width is always constant at 7.5H. Therefore, this reference signal VR and the previous frequency-divided output VD are added to the AND gate 35 of the phase comparator circuit 13, and a gate pulse Gp is generated only during the period when the phases of the two are shifted.

In the counting circuit 14, first, using this gate pulse Gp, the AND gate 36 gates the 2fH signal and extracts it.
A counter consisting of JK flip-flops 37 to 40 connected in cascade in four stages counts the number of 2fH signals taken out.

Then, when it is detected that the phase of the reference signal VR and the frequency-divided output VD is shifted by more than a certain amount, it is detected that nine or more 2fH signals are extracted and the phase is shifted by more than 4.5H. When the flip-flop 4 of the counter 40
Generates a reset control signal Rc from 0. When the reset control signal Rc is generated in this way, both signals VR
I:. Since it is determined that the phase of VD is out of phase, the set pulse generation circuit 15 generates a set signal RD from the frequency divider circuit synchronized with the vertical synchronization signal Vs, and this is generated by the frequency divider circuit 11.
The frequency dividing circuit 11 is reset so that the phase of the frequency-divided output VD matches the phase of the reference signal VR. When the amount of phase shift between the reference signal VR and the frequency-divided output VD is less than a certain amount of 4.5H, the resetting control signal Rc is not generated from the counters of the flip-flops 37 to 40, and it is determined that the shift is within the allowable range. Therefore, the frequency divider circuit 11 is not reset. Therefore, even if there is a slight jitter in the vertical synchronizing signal Vs, the frequency dividing circuit will not be set each time. In this way, in this device, a synchronizing operation is performed to match the phase of the frequency-divided output VD of the branching circuit 11 with the vertical synchronizing signal Vs.

Since this device uses a counted 2fH signal as the reference signal VR, the pulse width of the reference signal VR is always constant and does not depend on the reception condition of the television signal, jitter, circuit drift, etc. V1 is not affected and a stable vertical deflection operation can be obtained.
Further, by obtaining a stable vertical reference signal VR in this way, it is possible to increase the margin against fluctuations in the received signal, and in this respect, stable vertical deflection can also be achieved. In addition, the phase of this reference signal VR and the frequency-divided output VD are compared, and the amount of phase shift is detected by counting the number of signals output from 2f1 using the comparison output, so that accurate phase shift can be detected. A detection operation can be achieved. In the above embodiment, the count value by the flip-flops 27 to 30 in the reference signal generating circuit 12 is set to 15, and 7.
．． I tried to obtain a reference signal VR with a pulse width of 5H, but
It goes without saying that this count value may be further increased or decreased to create a reference signal VR having a wider or narrower pulse width than the frequency-divided output VD.

However, in that case, it is necessary to set the counting circuit 14 accordingly. As described above, according to the present invention, it is possible to increase the margin of vertical synchronization even with respect to input signal jitter, drift, or circuit fluctuation, in addition to a vertical synchronization device using a frequency division method. This makes it possible to realize a device that operates stably and accurately.

[Brief explanation of the drawing]

The figure is a circuit diagram of a vertical deflection device according to an embodiment of the present invention. 6... Synchronization separation circuit, 7... Horizontal deflection circuit, 8...
・Vertical deflection circuit, 9...Cathode ray tube, 10...2fH
Generation circuit, 11... Frequency dividing circuit, 12... Reference signal generation circuit, 13... Phase comparison circuit, 14... Counting circuit,
15...Reset pulse generation circuit.

Claims (1)

[Claims] 1 An nf_H generation circuit that generates a signal with a frequency nf_H that is an integral multiple of the horizontal frequency f_H in synchronization with a horizontal synchronization signal extracted from a television signal, and a frequency-divided signal with a vertical frequency f_V that divides this nf_H signal. a frequency division circuit that generates a frequency, a reference signal generation circuit that counts the nf_H signal in synchronization with a vertical synchronization signal extracted from a television signal and generates a reference signal with a constant pulse width, and a frequency division circuit that generates a reference signal with a constant pulse width; A phase comparator circuit that compares the signals and generates a gate pulse during a period when the phases of the two are out of phase, gates and counts the nf_H signal using this gate pulse, and resets when the counted value is greater than a predetermined value. A counting circuit that generates a control signal, and when this reset control signal is generated, a reset pulse is generated in synchronization with the vertical synchronization signal, and this reset pulse resets the frequency divider circuit to convert the frequency division signal and the frequency divider circuit. 1. A vertical synchronization device, comprising: a reset pulse generation circuit that matches the phase with a reference signal; and vertical deflection is controlled using a frequency-divided output of the frequency divider circuit.