JPS6051300B2 - vertical deflection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to synchronization means for a device that divides a signal with a frequency that is an integral multiple of the horizontal frequency to create a signal for vertical deflection, and provides a device that can achieve accurate synchronization. This is what I am trying to do.

In a television receiver, a signal with a frequency nfH that is an integer multiple of the horizontal frequency fH is generated in synchronization with a horizontal synchronization signal, and this signal is synchronized with a vertical synchronization signal and then frequency-divided to obtain a vertical frequency f.
It is known to create a vertical deflection pulse of V and perform vertical deflection using this frequency-divided output pulse.

In such a device, the phase of the vertical synchronization signal extracted from the television signal is compared with the phase of the vertical deflection pulse obtained by frequency division, and when the phase of the two is shifted by more than a certain value, the vertical synchronization signal is output. By using this to reset the frequency divider circuit, the two phases are made to match. However, in the past, as a reset signal used in such cases, the vertical synchronization signal was waveform-shaped and then differentiated and used as it was, so there was a risk that an erroneous reset operation would occur, especially during playback on a video tape recorder. The drawback was that there were too many. That is, as shown in FIG. 1, in order to ensure accurate vertical synchronization without being affected by head switching, especially in the playback signal of a video tape recorder, a predetermined pulse is applied as shown in FIG. 1A. An auxiliary vertical synchronization signal with a width (usually 3 to 4H width) is inserted at a position prior to the head switching period, and is used to control the vertical synchronization of the receiver. When integrated by an integrator circuit, as shown in B, the part of this auxiliary vertical synchronization signal V and the part of the normal vertical synchronization signal after that (because the head is switched in this part, the disturbed noise signal is A large integrated output may be generated in both cases, and if this is shaped into a waveform at the level shown by the dashed-dotted line, it will become two vertical synchronization pulses as shown in C. Therefore, when this is further differentiated, two pulses for resetting the frequency divider circuit, such as D, are generated.
This causes the vertical synchronization to become unstable. In addition to receiving such playback signals from a video tape recorder, two or more reset pulses may be generated during the vertical blanking period and the frequency divider circuit may be reset by mistake in the reception state in a weak electric field. Sometimes it happens. Therefore, the present invention eliminates such conventional drawbacks, and accurately generates only one reset pulse for resetting the frequency dividing circuit for generating vertical deflection pulses, thereby making it possible to accurately perform vertical deflection operation. The purpose of this is to provide a device that enables the generation of reset pulses for a certain period of time after a predetermined vertical synchronization pulse is generated and a reset pulse is created. It is characterized by:

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof.

FIG. 2 shows its circuit diagram, and FIG. 3 shows its waveform diagram at each part. In Figure 1, 1 is an antenna, 2 is a tuner, 3
is a VIF circuit, 4 is a video detection circuit, 5 is a signal processing circuit that amplifies the luminance signal and reproduces the color signal, 6 is a synchronization separation circuit, 7 is a horizontal deflection circuit, 8 is a vertical deflection circuit, and 9 is a cathode ray tube. , these are similar to those of general television receivers. In addition, 10 is a horizontal frequency FH (:1
5.75KHz), a 2fH generation circuit that creates a 2fH signal with a frequency twice that of 5.75KHz.
A frequency dividing circuit 12 integrates a composite synchronizing signal as shown in FIG. 1A extracted from a television signal. 13 is a waveform shaping circuit that shapes the waveform at the level indicated by the dashed line and generates a pulse like C. On the other hand, 15 is a waveform shaping circuit 13
A phase comparator circuit 16 compares the phase of the output C of the frequency divider circuit 11 with the phase of the divided output of the frequency divider circuit 11, that is, the phase of the vertical deflection I pulse, and generates a reset gate signal only when the two are different from each other. A reset signal generation circuit 17 is used to reset the frequency divider circuit 11 only by the first pulse C for vertical synchronization and not to reset it by the later pulses. This is a gate that generates a reset pulse for resetting.

Next, the detailed configuration and operation of these circuits will be explained with reference to the waveform diagram of FIG. 3.

First, in the frequency dividing circuit 11, the frequency of the 2fH generation signal E from the 2fH generation circuit 10 is divided into 1 of 52 using flip-flops 18 to 27 connected in m stages and a NAND gate 28, so that the pulse width is 7. 511 (however, H is the horizontal period =
1/FH) and generates a vertical deflection pulse with a vertical frequency Fv. This divided output is applied to the vertical deflection circuit 8, which supplies a sawtooth wave current for vertical deflection to the vertical deflection coil. 1. On the other hand, the reset signal generation circuit 16 includes a counter consisting of flip-flops 29 to 32 that count the 2fH signal E, an R-S flip-flop 33 and a NAND gate 34 controlled by the counting output thereof, and a differentiating circuit for generating a reset pulse. It consists of 35 and -.

First, the shaping pulse C from the waveform shaping circuit 13 is applied to the flip-flops 29 to 33, thereby resetting them all, and from the time when the pulse C disappears, 2 fH
The signal E starts counting, and each flip-flop 29 to 3
2 generates counting outputs such as F~I. When this counter counts the period of time, an output like J is generated from the NAND gate 34, thereby setting the flip-flop 33. Thus, flip-flop 3
3, it is possible to obtain only one output, such as K, whose leading edge coincides with the first leading edge of the vertical synchronizing pulse C during the vertical blanking period. Therefore, by applying this output K to the differentiating circuit 35, only one reset pulse like L is created, and this is applied to the frequency dividing circuit 11 via the gate 17. In this way, the frequency divider circuit 11 can be reset only once during the vertical blanking period, and the vertical deflection of the receiver can be precisely synchronized with the vertical synchronization signal of the received signal. That is, by using the output of the NAND gate 34, the flip-flop 33 is prevented from being set even if the vertical synchronizing pulse C is generated again during the period after the vertical synchronizing pulse C disappears. It is possible to prohibit the second and subsequent reset pulses from being generated during this period. As described in detail above, according to the present invention, even when receiving a playback signal of a video tape recorder or receiving a weak electric field broadcasting signal using a frequency division type vertical deflection device, the same vertical blanking period can be used. In the middle, generation of a reset pulse is prohibited for a certain period of time after the vertical synchronization pulse disappears after the first reset pulse is generated, so that the frequency divider circuit can be accurately reset and vertical synchronization can be performed. A useful device can be obtained which can be synchronized to a synchronization signal.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the operation of a conventional vertical deflection device, FIG. 2 is a circuit diagram of a vertical deflection device according to an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining its operation. be. 6... Synchronization separation circuit, 8... Vertical deflection circuit, 10... 2fH oscillation circuit, 11...
...Frequency dividing circuit, 12... Integrating circuit, 13...
...Waveform shaping circuit, 15...Phase comparison circuit, 16...
...Reset signal generation circuit, 17...Gate.

Claims (1)

[Claims] 1. An nfH generation circuit that generates a signal with a frequency nfH that is an integral multiple of the horizontal frequency in synchronization with a horizontal synchronization signal separated from a television reception signal, and divides this nfH signal to generate a vertical deflection pulse of a vertical frequency. A frequency dividing circuit that
an integrating circuit that integrates the composite sync signal separated from the television reception signal; a waveform shaping circuit that shapes the integrated output into a waveform to generate a vertical sync pulse; a reset pulse generation circuit that generates a reset pulse during a blanking period;
A prohibition that is controlled by the vertical synchronization pulse and prohibits the generation of a reset pulse during the same vertical blanking period until a certain period of time elapses after the vertical synchronization pulse disappears after the first reset pulse is generated. 1. A vertical deflection device comprising: a circuit, wherein the frequency dividing circuit is reset by the reset pulse.