JPS5913119B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a shift-controlled storage device that can be easily integrated and can effectively increase storage capacity.

Shift registers exist as shift-controlled storage devices, and the shift registers used in the past are configured to store one bit of information using two storage elements.

That is, 52 clock pulses φ1 and φ2 with different phases are used for shift control, the gate of the first switch element is opened by the clock pulse φ1, input bit information is written to the first storage element, and the clock pulse φ2 is used. The bit information written in this first storage element is transferred to the second storage element by a second switch element which is gate-controlled by the gate, and the bit information written from this second storage element is transferred to the Read out in stages. In other words, a shift register is constructed by sequentially reading a large number of 1-bit memory units each having a pair of memory elements15, and the number of memory elements is at least twice the number of bits that can be stored. Requires a number. This memory element uses a semiconductor element such as a field effect transistor that can effectively use a gate capacitance as a storage medium.
Even if an attempt is made to construct a shift register using SI, the number of semiconductors to be integrated increases, making it difficult to construct a large-capacity shift register. This invention was made in view of the above points, and it is possible to reduce the number of memory elements per hit, and also to effectively improve the integration density, making it possible to increase the capacity by making it into an LSI. The present invention aims to provide a storage device that allows shift control to be performed easily.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its configuration. This storage device is made up of a plurality of storage bodies Ila, Ilb... connected in series, and each of the storage bodies Ila, Ilb... Switching circuits 12a, 12b, . . . are provided.
That is, input information is coupled to the memory Ila via the switching circuit 35 path 12a, and output information from the memory Ila is transmitted to the memory Ilb via the switching circuit 12b. In addition, each memory body 11a, 11b,
The output information signals of... are output from shift circulation circuits 13a and 13b.
The corresponding switching circuits 12a, 12 via...
The information is fed back to the storage units 11a, 11b, . . . , and the information is stored and held in circulation in each of the storage bodies 11a, 11b, . That is, when the switching circuits 12a, 12b, . . . select the previous information line, the storage bodies 11a, 11b, . By selecting the shift circulation circuits 13a, 13b, . . . in the circuits 12a, 12b, . These switching circuits 12a, 12b,
The switching command control for . . . is performed by the dynamic D or static S instruction circuit 14. A plurality of storage bodies 11a, which constitute a shift register in this way,
11b... are constructed by connecting five storage units 15a to 15e in series, for example, as represented by the storage unit 11a, and are specifically constructed as shown in FIG.

That is, each memory unit 15a to 15e is provided with one memory element T1 to T, respectively, and each of the memory elements T1 to T5 is composed of, for example, a field effect transistor having a gate capacitance. and 1 each
They are capable of storing bit information and are arranged in series so that the stored information is sequentially coupled to the next storage element. Each of the memory elements T, -T5 has a switch element T formed of a field effect transistor in series with its source and drain electrodes. ,~TO
5, T,, ~Tl5 are connected, and the switch element Tl
, ~T,5 are connected to ground point 01. And switch element T. , clock pulse φ10 is applied to the gate electrode of , φ1 is applied to Tl5, φ2 is applied to TO4, and φ is applied to Tl4.
3,..., φ, is coupled to Tll. In this case, clock pulses φ1 to φ,o are generated in this order with different phases as shown in FIG.
Clock pulses φ3, φ6, φ are applied to l to TO5, respectively.
4, the signal potential GG based on φ2φ10 is coupled. In addition, the switching circuits 12a, 12b, .
The storage element T22 has a storage element T22 to which the signal from 3a is coupled, and each of the storage elements T2l and T22 is connected to a switch element T2.
3, connected together via T24, and grounded via switch element T25.

In this case, in the case of the dynamometer or static instruction circuit 14, the line 14a is
A signal of [1] of the potential GG is generated in the static state, and a signal of [1] is also generated in the line 14b during the static state. as a gate signal. Further, a clock pulse φ is coupled to the switch element T25 as a gate signal.
Furthermore, a switch element T26 to which bias power is applied in response to clock pulses φ and o is coupled to the storage elements T2l and T22. In the memory body 11a configured as described above, five memory units 15a to
For example, at the timing when clock pulses φ and o are generated, the four bit information are stored in the gate capacitors of the storage elements T1 to T4 of the storage units 15a to 15d, respectively. has been done.

Then, when clock pulse φ10 is applied in this state, switch element T is activated. The gate of T5 is opened, and the drain of storage element T5 is charged with potential VGG due to clock pulses φ and o.

Then, the gate of the switch element T5 is opened by the clock pulse φ.
Controlled by the state of information stored in the drain of 4,
For example, when information "1" is stored in the drain of the memory element T4, the gate of the memory element T5 is open;
The gates of the switch elements T, 5 are opened, and the potential GG previously charged in response to the clock pulse φ10 is discharged to the ground potential. That is, the storage information of the storage element T5 is set to the "0" state. Conversely, when the stored information at the drain of the storage element T4 is "O", that is, when it is at ground potential, the gate of the storage element T5 is not opened, and the gate of the switch element Tl5 is opened by the clock pulse φ1. The stored information "1" in the gate capacitance portion of the storage element T5, which was previously powered up, is not discharged. That is, the polarity of the storage information in the previous storage element T4 is reversed, and the information is shifted to and stored in the storage element T5. Then, when clock pulse φ2 is generated, switch element T is activated.

4, the drain of the storage element T4 is charged to "1", and as the gate of the switch element Tl4 is opened by the cross pulse φ3, the polarity of the information stored in the drain of the previous storage element T3 is reversed, and the information is stored in the storage element T4 section. From then on, the stored information in the memory units 15a and 15b is shifted to the memory unit 1 in response to the generation of clock pulses φ4 to φ7.
5b and 15c, respectively, with their polarities reversed.

In addition, in the switching circuit 12a, the clock pulse φ1
0 opens the gate of switch element T26, and clock pulse φ1 opens the gate of switch element T25.

Here, for example, assuming that the dynamic or static instruction circuit 14 indicates a static state and a signal "1" exists on the line 14b, the switch element T2
4 gate is open, clock pass H, pass φ
10 is charged and stored in the memory element T22. That is, this switching circuit 12a is driven and controlled simultaneously with the final stage storage unit 15e, and when the clock pulse φ1 is next coupled, the switching circuit 12a changes its drive according to the state of the stored information in the storage element T4 of the storage unit 15d. As described above, the drain of the memory element T5 is controlled, and at the same time, the gate of the memory element T22 of the switching circuit 12a is controlled according to the state of the drain of the memory element T5. For example, memory element T
When the memory information of the drain of No. 4 is "1", the memory element T
The gate of T5 is opened, and the drain of this storage element T5 is discharged together with the clock pulse φ to become information "0".
Therefore, when the clock pulse φ1 is applied to the memory element T22, the gate signal becomes "0".
The information previously charged in response to clock pulse φ10
1" is not discharged, and the storage information of the storage element T22 becomes the state of "1". That is, 4-bit information is sequentially shifted by clock pulses φ1 to φ10, so that the polarity of the information at the input terminal and the output terminal of the memory 11a is matched, and a dynamic instruction is given by the instruction circuit 14. Sometimes, information is transmitted by sequentially shifting the storage bodies 11a, 11b, . . . via the switching circuits 12a, 12b, . That is, according to the memory device configured in this manner, a memory body that is shift-controlled is constructed by using five memory elements for, for example, 4-bit information, and a large number of these memory bodies are connected in series. By doing this, a long shift register is constructed, and for each of these storage bodies 11a, 11b,... Clock pulses φ1 to φ,o as shown
It is sufficient to combine them in parallel.

Therefore, the number of elements used per bit can be significantly reduced compared to conventional methods, which is extremely effective when constructing a shift register with a large storage capacity, and can replace cards, tapes, etc. This allows it to be effectively used as a storage medium. More importantly, each of the memory bodies 15a to 15e is composed of a semiconductor element such as a series of field effect transistors with source and drain electrodes connected to each other, and as in the past, a transfer gate is provided between each memory unit. do not need.

Therefore, the circuit connections between each semiconductor element can be simplified,
Furthermore, since each semiconductor element can be arranged efficiently, it can be effective in increasing the density. That is, LSI
This is particularly effective when configuring a large-capacity shift register. Here, in the above embodiment, in order to drive the five memory units 15a to 15e, 10
Although five clock pulses φ1 to φ10 are used, it is possible to use five clock pulses φ1 to φ5 by configuring as shown in FIG.
That is, the switch element T. l~TO5 and Tll~
T, 5 are connected to common bias lines 18, 19, respectively, bias line 18 is connected to power supply GG via switch element Tp, and bias line 19 is connected to ground GND via switch element TD. And switch element T
p and TD are gate-controlled by pulses P and D, respectively, and these pulses P and D are generated so as to divide each of the clock pulses φ1 to φ5 into two as shown in FIG. Then, the clock pulse φ, is applied to the switch element TO59Tll, φ2 is applied to the TO49Tl5, and φ3 is applied to the switch element TO59Tll.
O39Tl4, φ4 is T. 2, Tl3, φ5 is T.

For example, when clock pulse φ1 is being generated, lines 18 and 19 are time-divided by pulses P and D to
? and GND to produce the same effect as in the case of using 10 clock pulses in the previous embodiment.
In this case, lines 18, 19 are connected to a large number of storage bodies 11a, 1
1b..., so the control signal line can be further simplified. Also, as shown in FIG. 6, a switch element T is provided.

Switch elements TPl to TP,, T
Dl to TD5 are interposed in series, and this switch element T
p, ~TP5, TD, ~TD5 as the pulses P and D
The same implementation is possible by controlling the gates using clock pulses φP and φD corresponding to . Further, as shown in FIG. 7, memory elements T1 to T5 and a switch element T are provided.

l~TO, switch elements T3l~T3 between each
5 is interposed, and the switch elements T3l to T35 are connected to the eighth
As shown in the figure, gate control may be performed by clock pulse φP1 generated at timings between clock pulses φ1 to φ5, respectively. That is, the switch element T in this example. l~TO, also acts as a memory element, for example, the clock pulse φ
5 makes the switch element T. When a gate signal is given to 5, the voltage GG is switched to the switch element T.

, is charged between the source of the switch element T35 and the drain of the switch element T35, and when the clock pulse φP1 is generated, the above-mentioned charge potential GG is shifted and stored in the storage element T5 via the switch element T3. Discharge is controlled according to the information content, and pit information is shifted between memory units. In the above embodiment, the five memory units 15a to 15d constitute the memory bodies 11a, 11b..., and the memory bodies 11a, 11b...
2a, 12b, . . . , and dynamic and static switching is performed under the control of the ratio converter circuits 12a, 12b, . As shown in FIG. 9, the switching circuit is omitted and the storage bodies 11a and 11b are
... may be directly connected in series.

In FIG. 9, the same components as in FIG. 1 are designated by the same reference numerals. As described above, according to the present invention, it is possible to obtain a storage device that is effective in reducing the number of storage elements per bit and increasing the capacity of a shift register. It is highly effective in simplifying the configuration and improving the integration density when integrated into LSI, so it is even more effective in increasing capacity and downsizing, and can be used as an information storage device instead of storage media such as cards and tapes. It can be effectively used as

In the embodiment, 4 bits of information are stored in one memory, but the capacity of this memory can be set arbitrarily.

However, if one memory is set to a capacity of 1 byte,
Effective for input/output control. As mentioned above, it goes without saying that the present invention is not limited to the matters described above, and can be applied in various ways without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram illustrating a memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing one of the memory bodies of the above embodiment, and FIG. 3 is a circuit diagram showing a circuit for driving the above memory body. 4 is a circuit diagram showing another example of the structure of the memory, FIG. 5 is a diagram showing the clock pulse for driving the memory shown in FIG. 4, and FIGS. FIG. 8 is a diagram showing clock pulses for driving the memory shown in FIG. 7, and FIG. 9 is a diagram showing another embodiment of the present invention. 11a, 11b... Memory body, 12a, 12b.
...Switching circuit, 13a, 13b...Shift circulation circuit, 14...Dynamic, static instruction circuit, 17...Timing generator.

Claims (1)

[Claims] 1. A memory element made of a semiconductor, a first switch element that couples a charging potential to this memory element, and a potential stored via this first switch element that corresponds to an information potential coupled to the memory element. A second switch element for discharging n memory units that is one more than the number of bits of bit information composed of a plurality of bits, each of which is equipped with a second switch element for discharging, and whose respective memory potentials are used as information potentials for the next stage memory element. n stages are connected in series so as to be coupled, and a gate signal to be supplied to the memory unit, each of the first switch element and the second switch element is transmitted from the output stage side of the memory unit to the first switch. The time is sequentially given to the element and the second switch element at different times depending on the order of the elements, and the n-1 bit information is sequentially transferred to one bit from the memory unit on the output stage side by the memory units connected in n stages in series. A storage device characterized in that the storage device is configured to store data by shifting the drive.