JPS5914836B2 - information storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION 5 The present invention relates to a shift-controlled information storage device that is improved by reducing the number of storage elements per bit and by simplifying the control system.

Many devices have been considered for storing information, but the shift register is known as a device that can easily input and output information. ι This shift register is a memory that stores 1 bit of information. A large number of storage units are connected in series and driven so that bit information is sequentially transmitted between storage units, and is often used as a buffer register, control register, etc. in various information processing devices.

The storage unit constituting such a shift register is constructed using two storage elements, and is driven and controlled using two clock pulses φ1 and φ2 having different phases. That is, two 20 memory elements are arranged in series, a switch element is provided on the input side of each memory element, and the switch elements are gate-controlled by clock pulses φ1 and φ2 that are generated at different times. First, gate 25 of the first switch element is opened with a clock pulse φ1, and the input bit information of the previous stage is stored in the first storage element. Then, the gate of the second switch element is opened, and the bit information stored in the first storage element is transmitted to and stored in the second storage element. A read output signal to the stage is obtained. That is,
Such a shift register consisting of a single memory unit requires two memory elements per bit and a write control circuit for each of these memory elements, so increasing the memory capacity requires This requires a very large number of elements.

For this reason, when making it into an LSI and solidifying it to have an O, n configuration,
There is a limit to its storage capacity, and it is difficult to set it to a large capacity that allows it to be used, for example, for information storage.

This invention has been made in view of the above points, and it is possible to reduce the number of memory elements per bit and to effectively improve the integration density especially when integrated into an LSI. The purpose of the present invention is to provide an information storage device that also simplifies the process.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its basic configuration, and shows a case where it is composed of five storage units 11a to 11e. The memory units 11a to 11e each have memory elements T1 to T5 made of field effect transistors having gate capacitance, and the gate electrodes of each of the memory elements T1 to T5 are controlled by the drain voltage of the previous stage memory element. connected in series with the signal so that In addition, first switch elements TOl to TO5 and second switch elements Tll to Tl, which are field effect transistors, are connected to the source and drain electrodes of the memory elements T1 to T5, respectively.
5 is connected, the second switch element Tll~T,5 is connected to ground (GND), and the clock pulses φ1, φ3,
The gates are controlled by φ5, φ7, and φ9. Further, the gates of the first switch elements TOl to Tll are controlled by clock pulses φ, 0, φ2, φ4, φ6, and φ8, respectively, and the potential GG generated by the corresponding clock pulse is coupled at the time of gate control. Here, the clock pulses φ1 to φ10 are generated sequentially at different times as shown in FIG.
) is a signal that changes between the potential and VGG. That is, in a memory device configured in this way, first, when clock pulses φ,o are applied, the switch element TOl
The gate of the clock pulse φ10 is opened, and the potential VGG of the clock pulse φ10
is coupled to the drain of storage element T1.
The drain of the battery is charged with the potential GG.

That is, the drain, which is the output part of this memory element, is in the state of information "1". Next, when clock pulse φ1 occurs, the gate of switch element Tll is opened. At this time, the memory element T. When the storage information of the previous stage storage element T2 is "1", a gate signal is given to the gate of l.
When it is "O", the gate signal is not applied. Therefore, when the gate signal is applied, the source and drain of the storage element T1 are in a conductive state, so when the gate signal is applied to the switch element Tll,
The potential GG previously charged in the gate capacitor is grounded (GND
The information stored in the gate capacitance portion of the storage element T1 becomes "O" after being discharged to the bottom. Furthermore, when the gate signal is not applied to the gate of the storage element T1, the switch element Tl
Even if the gate of storage element T is opened, the gate of storage element T is not opened, and the potential VGG charged in its gate capacitor is held as it is, and the storage information is set to "1". That is, the information stored in the drain of the previous storage element T2 is shifted to the storage element T1 with its polarity reversed in response to the clock pulse φ1. Then, when the tarlock pulse φ2 is applied, the potential GG is charged to the drain of the storage element T2 via the switch element TO2, and the information stored in the drain of the storage element T3 at the previous stage in response to the clock pulse φ3 is charged. The polarity is inverted and shifted to the storage element T2.

Thereafter, in response to clock pulses φ4 to φ, which are sequentially generated, the information stored in the gate capacitances of the memory elements T5 and T4 is reversed in polarity and shifted to the memory elements T4 and T3, and the data input is transferred to the memory element T5. It will be in the state where it will be written. That is, in a state where there is always one memory unit that is in the “empty” state, the previous information is shifted to this memory unit that is in the “vacant” state, and the five memory units 11a to 11a.
11e stores 4-bit information and performs shift control, thereby forming one set of memory.

A long shift register is constructed by arranging a large number of memory bodies in series and driving these memory bodies in parallel with clock pulses φ1 to φ10. According to such a storage device, each of the storage units 11a to 11e for storing 1-bit information is composed of a plurality of field effect transistors whose sources and drains are connected in series. Necessary circuit elements can be integrated and wired in a superimposed state for each memory unit.

Therefore, the integration density can be made sufficiently high, wiring can be done easily, and one piece of bit information can be stored with one storage element. It is possible to perform LS conversion effectively and has a great effect in increasing its storage capacity. However, as it is, if the memory body is composed of five memory units as shown in the figure, 1
Zero clock pulses φ1 to φ10 are required, and a wiring circuit for this is also required, which is an obstacle to miniaturization and integration. Therefore, the present invention has further improved the above points, and one embodiment thereof will be described with reference to FIG. 3.

In FIG. 3, the same components as in FIG.
is constructed in the same way as in FIG. The switch elements TOl-TO5 are connected to the charge bias line 12, and the switch elements Tll-Tl5 are connected to the discharge bias line 13, respectively. The quack pulses used here are five quack pulses corresponding to the number of memory units 11a to 11e, which are generated sequentially at different times as shown in FIG.
The tarlock pulse φ1 is coupled to the switch elements TO2 and Tll as a gate signal.

In addition, the clock pulse φ2 is applied to the switch elements TO3 and Tl.
2, φ3 is T. 4, Tl3, φ4 is TO5, TI4
, φ5 is TOl, Tl. are respectively supplied as gate signals.

And charging and discharging bias lines 12, 13
, switch elements Tp and TD are provided respectively,
A power supply potential GG and ground (GND) circuit is formed via these switch elements Tp and TD. Here, for the gate electrodes of the switch elements Tp and TD, pulses P and D, which time-division clock pulses φ1 to φ5, respectively, are combined with the gate signal, as shown in FIG. The potential GG is coupled to the bias line 12 at the timing, and the ground potential is coupled to the bias line 13 at the timing of the pulse D. That is, looking at the timing at which the clock pulse φ5 is generated, the gate of the switch element Tp is opened by the pulse P within the range of the clock pulse φ5, and the potential VGG is coupled to the bias line 12.

Therefore, the potential VG is applied to the gate capacitor portion of the storage element T1 via the switch element T whose gate is opened by the pulse φ5.
G is charged. Next, when the tarock pulse φ1 is generated, a gate signal is applied to the switch elements TO2 and Tll, and at the same time as the pulse φ1 rises, a pulse D is generated.
A bias line 13 is connected to the ground point.

Therefore, a discharge circuit is formed for the gate capacitance of the storage element T1 charged by the clock pulse φ5, and as explained in FIG. Discharge is controlled depending on the information content, and the information in the storage element T2 is shifted to the storage element T1 with polarity reversed. At this time, as mentioned above, the gate of the switch element TO2 is also opened by the clock pulse φ1, but at the above shift timing, the pulse P does not exist and the bias line 12 is in a floating state. , there is no effect on the information stored in the storage element T2. Then, when the pulse D ends and the pulse P is generated, the bias line 12 is activated by the switch element Tp.
The potential GG is coupled to the switch element T2 via the switch element TO2 whose gate is opened by the clock pulse φ1.
The potential VGG is charged to the drain of. That is, the clock pulses .phi.1 to .phi.5 and the pulses P and D cooperate to perform the same operation as shown in FIG. That is, with this configuration, the number of clock pulses to be used is the same as that of a single memory, and the setting of the clock pulse circuit is sufficiently simplified, which is effective for LSI.

In addition, when a large number of memory bodies each consisting of a plurality of memory units are arranged in series, the bias lines 12 and 13 can be set in common for this large number of memory bodies, and the switch elements Tp and TD for this purpose are also set. It is sufficient to provide one set for the entire storage body, and the configuration for this purpose can be sufficiently simplified. Furthermore, when integrating circuits such as LSIs, it is relatively easy to configure multiple field effect transistors whose sources and drains are connected in sequence, and the circuit wiring for this is also relatively easy. can be made to do so.

Therefore, as shown in FIG.
between each TO5 and the charging bias line 14 to which the potential GG is coupled, and the switch elements Tll to Tl5.
Switch elements Tp, ~TP5, are connected between each and the discharge bias line 15 connected to the ground (GND).
The same effect can be achieved by interposing TDl to TD5. That is, the switch elements TPl to TP5 receive the clock pulse φP corresponding to the pulse P shown in FIG.
The switch elements TDl to TD5 are gate controlled by the clock pulse φD corresponding to the pulse D.
], and operates in the same manner as in the previous embodiment. In FIG. 5, the same components as those in FIG. 8 are given the same reference numerals, and the explanation thereof will be omitted. In the embodiment, five sets of memory units 11a to 1
1e, one set of memory bodies is purchased and 4-bit information is stored therein, but the number of memory units constituting one set of memory bodies can be arbitrarily selected.

However, when configuring a long shift register by arranging a large number of memory bodies in series, it is effective for input/output control if one set of memory units is set to be able to store 1 byte of information. For example, by forming a circulation circuit connecting the input and output terminals of each storage body, effective control can be achieved when driving in a static manner. Furthermore, when converting the embodiment shown in FIG. 3 into an LS, the structure can be made very simple by incorporating the switch elements Tp and TD into the external control circuit as necessary. Furthermore, various modifications and applications are possible without departing from the gist of the invention. As described above, according to the present invention, a storage device that is effectively shift-controlled to increase storage capacity can be obtained, and furthermore, it is possible to solidify LSI etc. and simplify control loops. This is extremely effective when configuring an information storage device in place of cards, tapes, etc., for example.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram illustrating a basic form of the present invention, FIG. 2 is a diagram showing drive pulses for the basic form, and FIG. 3 is a circuit diagram illustrating an information storage device according to an embodiment of the present invention.
FIG. 4 is a diagram showing one drive pulse used in the above embodiment, and FIG. 5 is a diagram showing another embodiment of the present invention. 11a-11e...Single memory, 12, 14...
...Charging bias line, 13, 15...
Discharge bias line, T1-T5...Storage element, TOl-TO5, Tll-Tl5...Switch element.

Claims (1)

[Claims] 1. A memory element made of a semiconductor, a first switch element that couples a charging potential to the memory element, and a potential stored via the first switch element that corresponds to an information potential coupled to the memory element. The storage potential of the storage element is sequentially transferred to the storage element of the next stage. n stages are connected in series so as to be coupled as an information potential, and a charging potential is commonly supplied to the first switch element of each of the n memory units, and further a second switch of each of the n memory units is connected in series. A discharge potential is commonly supplied to the elements, and the gate of the first switching element of each memory unit and the gate of the second switching element of the adjacent memory unit on the output stage side are connected to the memory unit. A common gate signal is connected to each memory unit, and this gate signal is sequentially supplied at different times from the output stage side of the memory unit, and the charging potential and the discharging potential are supplied with the gate signal. Each time, the order of discharging and charging is generated at different times within that time range, and n-1 bit information is sequentially transferred to the output stage side by 1 bit using n memory units connected in n stages in series. An information storage device characterized in that data is stored by shift driving.