JPS5914832B2 - voltage sense circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to semiconductor memory devices (mask ROM, PROM, etc.)
The present invention relates to a voltage sensing circuit.

Figure 1 shows a mask ROM (Road Only Memory).
) is a basic configuration example of a semiconductor memory device used in 16
shows the case of a bit storage device. That is, the row decoder 1 selects one of the 128 input lines (row selection lines) of the memory cell array 2 using seven address lines A0 to A6. The cell array 2 has 8 blocks each consisting of 16 output lines, and a total of 128 output lines. The column selector 3 can select one of the output lines (16 lines) of each block using four selection lines A7 to Alo. The voltage sense circuit 4 calculates the logical sum of the output lines for each block, detects the logical level of the output data obtained for each block, converts it into 8-bit data, and sends this 8-bit data to the output buffer circuit. 5. 5 The voltage sense circuit 4 is
As shown in FIG. 2, the 16 output lines L1 to LIO from the column selector are input to the NOR circuit 11, and the voltage sense circuit 4 is provided with eight circuits as shown in FIG.

FIG. 3 shows the actual implementation of the circuit shown in FIG. 2 using MOS transistors, in which a depletion type load MOS transistor 12 is used in common, and a driving MOS transistor 13 is connected to the depletion type load MOS transistor 12.
1 to 1316 parallel circuits are connected. The gate inputs of these transistors 131 to 1316 are connected to the output lines L1 to L.
It is 16. 15 FIG. 4 shows the configuration of FIG. 1 in more detail, and only the output line (digit line) L is shown here.

A load transistor 12 and a driving transistor 131 connected in series between the power supply VDD and ground form an inverter 14, and a depletion type load MOS transistor 16 and a driving MOS transistor (enhancement Type) 17 forms an inverter 15, which inverts the output of the inverter 2514 supplied to the gate of the driving transistor IT. of the inverter 14,
A depletion type transistor 18 serving as a ROM load is connected between the output line Li connected to the gate of the driving transistor 131 and the power supply VDD, and a memory cell such as an enhancement type MOS transistor 19 is further connected to the output line Li. Multiple connections are made. Connected to the gate of cell 19 is row selection line ti. by the way,
In the circuit shown in FIG. 4, the inverter 35 of the sense circuit 4 detects the data read out to the output line Li when the level change of the output line Li exceeds the circuit threshold voltage of the inverter 14. It is.

However, the ROM load 18 and the ROM cell 19 are limited by the current consumption consumed by them and the area occupied by these elements within the integrated circuit, so the voltage level fluctuation of the output line L1 is very gradual and However, the circuit configuration shown in FIG. 4 has a problem in that it requires a long access time. The present invention has been made in view of the above-mentioned circumstances, and it makes the threshold voltage of an inverter circuit that detects voltage level fluctuations of the output line of a memory cell array variable, and changes this threshold voltage at an appropriate timing. The present invention is intended to provide a voltage sensing circuit in which the acceleration time can be improved.

An embodiment of the present invention will be described below with reference to FIG.

Since this embodiment is a partial improvement of the circuit configuration shown in FIG. 4, corresponding parts are given the same reference numerals and their explanation will be omitted. The feature of this embodiment is that a feedback circuit is provided which connects the output A of the inverter 15 to the gate of the load transistor (depression type) 12 of the inverter 14 via depletion type MOS transistors 21 and 22 as delay elements. . Next, the operation of the circuit shown in FIG. 5 will be explained.

If the output line L1 is now at 81゛ (high) level, then
Since the transistor 131 is on (conducting) and the point a is at the 10° (low) level, the transistor 17 is off (non-conducting) and therefore the output point b of the inverter 15 is at the "1" level. At this time, since the depletion type transistor 12 is driven by the gate input at the 81'' level, the apparent β of the inverter 14 becomes small.
However, β is the ratio of the current amplification factor of the transistor 131 and the current amplification factor of the transistor 12. As this β becomes smaller, the circuit threshold voltage of the inverter 14 becomes higher, and when the gate input of the transistor 13 changes from the "1" level to the "O" level, the inverter 14 easily performs an inverting operation. The time required for inversion is short. Figure 6 shows the input/output characteristics of the inverter 14, and the fact that the circuit threshold voltage Vth has become higher means that the circuit threshold voltage has moved from Vth to Vthl. It can be seen that it can be quickly reversed when the input voltage Vin moves from a high side to a low side.On the other hand, when the output line L1 is at the "0" level,
Transistor 131 is off and transistor 17 is on, so the gate input of load transistor 12 is at 0 level.

For this reason, the apparent β of the inverter 14 becomes large, the circuit threshold voltage becomes low, and the gate and gate inputs of the transistor 131 reach the 099 level, and the current from l/ to the current Fr
When changing to level 9, the inverter 14 easily performs the inverting operation, and the time required for inverting is short. Looking at this in FIG. 6, this corresponds to the fact that the circuit threshold voltage has reached Vth2. On the other hand, transistors 21 and 22 of the feedback circuit delay transmission of the output at point b to the gate of transistor 12. This is R.O.
It is well known that when the address specification of M changes, due to the circuit configuration of the column selector 3, a phenomenon occurs in which another address is specified and then the target address is specified. This is to avoid this period and change the circuit threshold voltage of the inverter 14 when the voltage of the output line L1 is stabilized even if the level of the output line L1 is about to change. Note that the transistor 131 in the circuit of FIG. 5 includes transistors 132 to 13 in FIG.
16 are connected in parallel, inverter 15, delay element 21,
22, load element 12, etc. are used in common. Further, the delay elements 21 and 22 are not limited to MOS transistors, but may be other circuits as long as they use elements that delay feedback signals. Also, the load MOS transistor 12
Although a depletion type MOS transistor was used as the MOS transistor, an enhancement type MOS transistor and a depletion type MOS transistor were connected in parallel, the gate of this depletion type transistor was connected to the output terminal of the inverter 14, and a feedback signal was input to the gate of the enhancement type transistor. The present invention is not limited to the embodiments and can be applied in various ways. As explained above, according to the present invention, the circuit threshold voltage of an inverter is moved in a direction that can be detected in the initial state when a change in the level of the input voltage to the inverter occurs, and the circuit threshold voltage is Since the movement is performed after the input voltage to the inverter is stabilized, an improvement in access time can be expected.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of a semiconductor memory device, Figure 2 is a block diagram showing the configuration of a semiconductor memory device.
4 through 4 are partially detailed circuit diagrams of the same configuration, FIG. 5 is a circuit diagram of an embodiment of the present invention, and FIG. 6 is an inverter input/output characteristic diagram showing the operation of the same circuit. L1... Output line (digital line), 12...
...depression type load MOS transistor, 1
31..., driving MOS transistor, 14,
15... Inverter, 21, 22...
delay element.

Claims (1)

[Claims] 1. A first inverter circuit including a load MOS transistor and a drive MOS transistor whose gate input is the output of the memory cell array, a second inverter circuit that inverts the output of this inverter circuit, and a second inverter circuit that inverts the output of this inverter circuit. A voltage sensing circuit comprising: a delay circuit that delays an output and feeds it back to the gate of the load MOS transistor.