JPH0766679B2 - Data output circuit - Google Patents

Description

The present invention relates to a data output circuit for taking out data from a storage element such as a ROM.

[Conventional technology]

Conventionally, a data output circuit in a memory device has a NOR circuit 6 connected to a bit line 4 of a ROM 2 as shown in FIG.
The output of the circuit 6 is passed through the transmission gate, that is, after the inverter 8 is inverted, the data output ▲ ▼ is output to the data bus 10 through the analog switch 9 which permits the signal to pass in response to the clock pulse φ or the inverted clock pulse. Occur.

[Problems to be solved by the invention]

In such a data output circuit, since the bit lines 4 are normally routed, it takes a considerable time due to the floating capacitance and the resistance of transistors when all the bit lines 4 shift to the low (L) level. Is known, which causes delay in data output.

Therefore, the present invention is intended to speed up data output.

[Means for solving problems]

The data output circuit of the present invention, as illustrated in FIG. 1, transmits a data bus (10) for transmitting data when a plurality of bit lines (4) for taking out the data read from the storage means shift to a low level. A data output circuit for sending a data output indicating the transition to the low level to
1st which receives a clock pulse at its gate and switches
A transistor (24) and a series circuit of a plurality of second transistors (16, 18, 20, 22) whose gates are individually connected to the bit lines whose low level transitions are to be detected. A first switching circuit for extracting a data output by switching the first transistor and the second transistor by connecting a circuit in series with the first transistor, and the data output through the first switching circuit. Is added to the gate and a plurality of third transistors (28, 3) connected between the gate of the second transistor and the ground point are connected.
Second switching circuit (26) consisting of 0, 32, 34)
A fourth transistor (36) connected in series between the second switching circuit and a ground point to switch the gate by receiving the clock pulse, and the fourth transistor and the first switching A sixth transistor (38) which is connected between a fifth transistor (38) for receiving the data output at its gate from a connection point with a circuit and a power supply and which receives at its gate a clock pulse having a phase opposite to the clock pulse for switching It is characterized by including a transistor (40) and an output section for taking out a data output having a reverse phase relationship with the data output from a connection point of the fifth transistor and the sixth transistor.

[Work]

By doing so, it is detected that the level of the data output DB that is output when a plurality of levels of the bit line 4 starts to shift to the low level, and in that case, the bit line 4 It is possible to shift all levels of L to L level through the switching circuit 26 as quickly as possible.

〔Example〕

 FIG. 1 shows an embodiment of the data output circuit of the present invention.

As a storage element, for example, the data read from the ROM 2 is added to the data output circuit 12 via the bit line 4.

The data output circuit 12 includes a p-channel second transistor 16 and a transistor corresponding to each of the bit lines 4.
18, 20, and 22 are installed, each transistor 16-22 forms a series circuit, and the first transistor 24 is connected in series to the transistor 16 side of the series circuit. Transistor
24 has its source connected to a power supply and its gate has a clock pulse applied to it. That is, the transistors 16, 18, 20, and 22 that form a series circuit with the transistor 24 form a first switching circuit. Therefore, the transistor 24 repeats conduction and interruption by the clock pulse, and the data output DB from the bit line 4 is output from the data output point set on the drain side of the transistor 22 in synchronization with the clock pulse.

Then, at this data output point, when all the bit lines 4 start to shift to the L level and the level of the data output DB starts to shift to a specific level, the level of all the bit lines 4 becomes lower. A second switching circuit 26 is provided for shifting to the level. The switching circuit 26 is
The n-channel type third transistors 28, 30, 32, 34 are parallelized. The sources of the transistors 28 to 34 are grounded and the gates are shared, and the data output DB is added to the gates. ing. That is, each of the transistors 28 to 34 has a level of the data output DB when the entire bit line 4 starts to shift to the L level.
When the voltage exceeds the threshold voltage V _TH of, the conduction occurs, and the bit line 4 shifts to the L level by the conduction,
As a lower specific level, for example, the level is quickly changed to the ground level.

Then, the data output DB is applied to the gate of the fifth transistor 38 through the n-channel type fourth transistor 36 which repeats conduction and interruption by the clock pulse applied to the gate. The transistor 38 and the sixth transistor 40, which is switched by applying a clock pulse φ to its gate, are connected in series to form an output section including a clock gate (inverter), and the data output DB
The inverted data output (1) is taken out in synchronization with the clock pulse φ and is output to the data bus 10.

As described above, in the data output circuit 12 of the ROM 2, when the entire level of the bit line 4 shifts to the L level, the switching circuit 26, which is provided between the data output section and the bit line 4 to form a feedback circuit, When the level of the data output DB exceeds the threshold voltage V _TH of the transistors 28-34, the conduction of the transistors 28-34 causes the bit line 4
It is possible to shift all of them to the ground level as soon as possible.

〔The invention's effect〕

As described above, according to the present invention, when a plurality of levels of the bit line shifts to the L level, all the levels of the bit line shift to the L level as quickly as possible according to the level of the data output. Since the data output representing it can be taken out, the data output speed can be increased with a simple circuit configuration, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data output circuit of the present invention, and FIG. 2 is a diagram showing a conventional data output circuit. 4 ... bit line 10 ... data bus 12 ... data output circuit 16, 18, 20, 22 ... second transistor (first switching circuit) 24 ... first transistor (first switching circuit) 26 ... second switching circuit 28,30,32,34 ... third transistor 36 ... fourth transistor 38 ... fifth transistor 40 ... sixth transistor DB ... data output ▲ ▼ ... … Data output

Claims (1)

[Claims] 1. Data which, when a plurality of bit lines for taking out the data read out from the storage means shift to a low level, send a data output indicating the shift to the low level to a data bus for transmitting the data. An output circuit, which receives a clock pulse at its gate and switches
A plurality of second gates whose gates are individually connected to the bit lines which should be detected to shift to the low level together with
A first switching circuit for extracting a data output by switching the first transistor and the second transistor by connecting the series circuit in series with the first transistor, A second switching circuit comprising a plurality of third transistors connected between the gate of the second transistor and the ground while the data output is applied to the gate through the first switching circuit; A fourth transistor connected in series between the second switching circuit and the ground point to switch by receiving the clock pulse at the gate, and a connection point between the fourth transistor and the first switching circuit. Connected between a fifth transistor receiving the data output at its gate and a power supply And a gate is provided with a sixth transistor that switches by receiving a clock pulse having a reverse phase relationship with the clock pulse, and has a reverse phase relationship with the data output from a connection point of the fifth transistor and the sixth transistor. A data output circuit comprising: an output unit for taking out a data output;