JPS5915179B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5915179B2 JPS5915179B2 JP51072365A JP7236576A JPS5915179B2 JP S5915179 B2 JPS5915179 B2 JP S5915179B2 JP 51072365 A JP51072365 A JP 51072365A JP 7236576 A JP7236576 A JP 7236576A JP S5915179 B2 JPS5915179 B2 JP S5915179B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- insulating layer
- metal
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は金属バンプを有する半導体装置のより10有効
的製造方法に関するものであつて、金属膜を除去する際
に発生するパツトオ極近傍の汚染、腐蝕を積極的に防止
せんとするものであり、本発明の構成においてはパッド
電極近傍に酸化物層を形成せしめる事により、前記金属
膜の除去液に対し、15耐腐蝕性をもたせた製造方法を
提供せんとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a more effective manufacturing method for semiconductor devices having metal bumps, which actively prevents contamination and corrosion near the bumps that occur when removing a metal film. In the structure of the present invention, an oxide layer is formed in the vicinity of the pad electrode, thereby providing a manufacturing method that provides 15 corrosion resistance to the metal film removal solution. It is.
従来、回路素子が形成された半導体基板上に金属バンプ
を形成するための方法として第1図に示すような製造方
法が提案されている。Conventionally, a manufacturing method as shown in FIG. 1 has been proposed as a method for forming metal bumps on a semiconductor substrate on which circuit elements are formed.
すなわち、20シリコン等の半導体基板1上に形成され
たSiO2等の第1の絶縁層2に電極形成用のアルミニ
ウム膜を電子ビーム、抵抗加熱等の手段で5000〜1
0000Λ被着せしめ、電極部分3を残し他を除去せし
め、しかる後CVD法で形成されたS10225(以下
CVDSi02と略記する)膜4を5000〜1()0
00X被着し、前記電極部分3の一部を残し、他を除去
する。これを第1図aに示す。次いC複数層からなる金
属膜5を蒸着法により全面に形成するが、前記金属膜5
はCr■Cu、N卜30Cu、Cr−Nf−Cuもしく
はCr■−C叶AU、Ni−CIF−Au、Cr−Ni
−Cu等の複数層であつて同一の蒸着時に真空を止める
事なく順次に蒸着するものである。Cr又はNiはアル
ミニウムの電極部分3もしくはCVDSi02膜4との
密着力を高めるため35の膜であり、Cu又はCu−A
uはメッキ処理によるバンプの形成を容易ならしめるた
めの膜であつて、Cr、Niのそれぞれの厚さは約10
00Λ、Cuは1000〜5000λの膜厚を有する。
又、Cr,NiのかわりにTi膜を用いる事もある(第
1図b)。更に前記金属膜5上にメツキマスク用の感光
性樹脂6を前記電極部近傍に設け開孔部7を形成する(
第1図c)。That is, an aluminum film for electrode formation is formed on a first insulating layer 2 made of SiO2 or the like formed on a semiconductor substrate 1 made of 20-100% silicon or the like using an electron beam, resistance heating, or the like.
0,000 Λ was deposited, the rest was removed leaving only the electrode part 3, and then the S10225 (hereinafter abbreviated as CVDSi02) film 4 formed by the CVD method was coated with 5,000 to 1()0
00X deposition, leaving part of the electrode part 3 and removing the rest. This is shown in Figure 1a. Next, a metal film 5 consisting of multiple layers of C is formed on the entire surface by a vapor deposition method.
is Cr■Cu, N30Cu, Cr-Nf-Cu or Cr■-C AU, Ni-CIF-Au, Cr-Ni
- Multiple layers of Cu, etc. are deposited one after another without stopping the vacuum during the same deposition. Cr or Ni is a film of 35 to increase adhesion with the aluminum electrode portion 3 or CVDSi02 film 4, and Cu or Cu-A
u is a film to facilitate the formation of bumps by plating, and the thickness of each of Cr and Ni is approximately 10
00Λ, Cu has a film thickness of 1000 to 5000λ.
Also, a Ti film may be used instead of Cr or Ni (FIG. 1b). Furthermore, a photosensitive resin 6 for a plating mask is provided on the metal film 5 near the electrode portion, and an opening portion 7 is formed (
Figure 1 c).
しかるのち、前記金属膜5を一方の共通電極として、A
u又はCu,半田等を電着せしめ、金属バンプ8を形成
する(第1図d)。After that, using the metal film 5 as one common electrode,
U or Cu, solder, etc. are electrodeposited to form metal bumps 8 (FIG. 1d).
前記金属バンプを通常5〜20μmの高さに形惑し、終
れば、感光性樹脂6訃よび金属膜5の不i部分をエツチ
ングし除去し、第1図eの構造を得るものであつた。こ
の様な従来の製造方法においては、金属バンプ8の形成
後に複数層の金属膜5を除去するために、金萬膜の除去
液(エツチング液)、例えばCrであればフエリシアン
化カリウムとカセイソーダの混合液、Cuであれば強酸
を用いねばならない。このため金属バンプ8もエツチン
グされ所望の形状を消失してしまつたり、あるいは、長
時間のエツチングにより第1図eのA部にエツチング液
が浸透してしまい、金属バンプ8の接触面積を減少せし
め、付着強度を低下し、更にはCVDSiO2膜4にピ
ンホールが存在する場合には前記エツチング液により、
電極配線もしくは回路素子を損傷,汚染してしまい、信
頼性を著しく低下させるものであつた。本発明は上述の
従来技術の欠点に鑑みてなされたものである。The height of the metal bump is usually 5 to 20 μm, and when finished, the photosensitive resin 6 and the metal film 5 are etched and removed to obtain the structure shown in FIG. 1e. . In such a conventional manufacturing method, in order to remove the multiple layers of metal films 5 after forming the metal bumps 8, a metal film removal solution (etching solution), for example, in the case of Cr, a mixture of potassium ferricyanide and caustic soda is used. If the liquid is Cu, a strong acid must be used. As a result, the metal bumps 8 may also be etched and lose their desired shape, or the etching solution may penetrate into the area A in Figure 1 e due to long-term etching, reducing the contact area of the metal bumps 8. If there are pinholes in the CVDSiO2 film 4, the etching solution may
This would damage or contaminate the electrode wiring or circuit elements, significantly reducing reliability. The present invention has been made in view of the above-mentioned drawbacks of the prior art.
本発明の構成例を金属バンプとしてAuバンプを形成す
る場合について第2図で詳述する。A configuration example of the present invention in which Au bumps are formed as metal bumps will be described in detail with reference to FIG.
熱酸化法により形成されたSiO2膜12を有する半導
体基板11上に形成された回路素子(図示せず。)上に
第1の金属膜としてアルミニウム膜13を真空蒸着法に
より5000λ〜10000λの厚さに被着する。次い
で、前記アルミーウム膜13上に第1の絶縁物層14を
全面に被着する。前記第1の絶縁物層は感光性樹脂膜で
も良6・し、あるいは低温で形成したCVDSiO2膜
でも良い。前記第1の絶縁物層14によつてパット1極
に相当する部分のみを残存させたパターンを形成し、例
えば感光性樹脂膜パターンにより、前記アルミーウム膜
13の表面を陽極酸化しAl2O3膜13′を形成する
。前記感光性樹脂膜パターンのかわりにCVDSiO2
膜を用いれば、500℃の酸素雰囲気中、もしくは酸素
プラズマ雰囲気中にさらす事により、容易にAl2O3
膜13′を形成できる。前記M2O3膜13′は第1の
絶縁物層14の下面には形成されない。次いで前記第1
の絶縁物層14を除去し、パツト1極部分}よび、形成
された回路素子間を結ぶ配線部分を残存させるために、
第2の絶縁物層15として感光性樹脂膜を塗布し、パタ
ーン形成を行なう。前記第2の絶縁物層15で被覆され
ない部分は、Al2O3膜13//>S露出しているか
ら、H2O:H3PO4:CrO3=100cc:3。
5cc:29の80℃の溶液に浸せば、160λ/60
秒でAl2O3膜13/は除去され、次いでH3PO4
系の液に浸せばアルミニウム膜13も除去され第2図b
の構造を得る。An aluminum film 13 is deposited as a first metal film on a circuit element (not shown) formed on a semiconductor substrate 11 having a SiO2 film 12 formed by a thermal oxidation method to a thickness of 5000λ to 10000λ by a vacuum evaporation method. be coated on. Next, a first insulating layer 14 is deposited on the entire surface of the aluminum film 13. The first insulating layer may be a photosensitive resin film, or may be a CVDSiO2 film formed at a low temperature. A pattern is formed using the first insulating layer 14 in which only a portion corresponding to one pole of the pad remains, and the surface of the aluminum film 13 is anodized using, for example, a photosensitive resin film pattern to form the Al2O3 film 13'. form. CVDSiO2 instead of the photosensitive resin film pattern
If a film is used, Al2O3 can be easily removed by exposing it to an oxygen atmosphere at 500°C or an oxygen plasma atmosphere.
A film 13' can be formed. The M2O3 film 13' is not formed on the lower surface of the first insulating layer 14. Then the first
In order to remove the insulator layer 14 and leave the single pole part of the pad and the wiring part connecting between the formed circuit elements,
A photosensitive resin film is applied as the second insulating layer 15 and patterned. Since the portion not covered with the second insulating layer 15 is exposed to the Al2O3 film 13//>S, H2O:H3PO4:CrO3=100cc:3.
5cc: 160λ/60 if immersed in 29 80℃ solution
In seconds the Al2O3 film 13/ is removed and then the H3PO4
If the aluminum film 13 is immersed in the system liquid, the aluminum film 13 will also be removed, as shown in Fig. 2b.
obtain the structure of
又、前記Al2O3膜13′の膜厚は約3000λが望
ましい。不要となつた第2の絶縁物層15すなわち感光
性樹脂膜を除去し、更に第3の絶縁物層16を全面に被
着する。前記第3の絶縁物層16はCVDSiO2であ
つて、パツド電極のみを開孔させるために第4の絶縁物
層・感光性樹脂膜を塗布し、前記パツト1極のみを開孔
したパターンを形成、しかるのち、HF系の腐蝕液に浸
せば、パツト電極上の前記第3の絶縁物層は腐蝕され、
開孔し、更に前記第4の絶縁物層を除去すれば第2図c
′の構造を得る。前記工程に卦いて、第4の絶縁物層に
よつて開孔される大きさは、第1の絶縁物層14による
パターンと第2の絶縁物層の間にあつて、少なく共CV
DSiO2膜16によつて開孔された部分にAl2O3
膜13′が存在しなければならない。次いで、第2図c
の状態に第2の金属膜17を被着する。第2の金属膜は
本構成例に}いては0−α膜の場合、同一真空容器内に
おいてCr,lOOOλ,CrlOOO〜5000λと
順次に蒸着するものである。又、第2の金属膜の他の構
成を示せば、Ni−Cu,Ti−Ql,Cr−M−Cu
,Cr−Ti−01,Ni−01−Au,Ni−0】−
Au,Ti−Q1−Al,O−Ni−α−Au,Cr−
Ti−α―顛の構成を用いても良い。更に前記第2の金
属膜17上に第5の絶縁物層として感光性樹脂膜を塗布
し、パツト童極近傍のメツキする部分のみを開孔したパ
ターンを形成し次の工程でメツキ処理を実施するわけで
あるが、前記第5の絶縁物層により開孔し露出した第2
の金属膜17の表面は、工程中に汚染されたり、酸化物
の形成があり、これらはメツキ処理にち・いて不良の金
属バンプを形成する結果になる。Further, the thickness of the Al2O3 film 13' is preferably about 3000λ. The second insulating layer 15, that is, the photosensitive resin film that is no longer needed is removed, and the third insulating layer 16 is then deposited on the entire surface. The third insulating layer 16 is made of CVDSiO2, and in order to open only the pad electrode, a fourth insulating layer/photosensitive resin film is applied to form a pattern in which only one pad electrode is opened. , Then, by immersing it in an HF-based corrosive solution, the third insulating layer on the pad electrode is corroded,
If the hole is opened and the fourth insulating layer is removed, the result is shown in FIG. 2c.
′ is obtained. In the above process, the size of the hole formed by the fourth insulating layer is between the pattern formed by the first insulating layer 14 and the second insulating layer, and at least the size of the opening is equal to CV.
Al2O3 in the part opened by the DSiO2 film 16
A membrane 13' must be present. Then, Fig. 2c
The second metal film 17 is deposited in this state. In the case of the second metal film, which is a 0-α film in this configuration example, Cr, lOOOOλ, and CrlOOOO to 5000λ are sequentially deposited in the same vacuum vessel. Other configurations of the second metal film include Ni-Cu, Ti-Ql, Cr-M-Cu
, Cr-Ti-01, Ni-01-Au, Ni-0]-
Au, Ti-Q1-Al, O-Ni-α-Au, Cr-
A Ti-α-frame structure may also be used. Further, a photosensitive resin film is applied as a fifth insulating layer on the second metal film 17, and a pattern is formed in which only the portion to be plated near the pad dowel is opened, and the plating process is performed in the next step. However, the second hole opened and exposed by the fifth insulating layer is
The surface of the metal film 17 may be contaminated or have oxides formed during the process, which results in the formation of defective metal bumps after the plating process.
したがつて、アセトン,トリクレン等の有機溶剤により
洗浄を行ない1〜10%HCI溶液に浸し酸化物の除去
を行なう。例えば、5%HCI溶液に5秒浸せば、Cu
表面は100〜200λ除去され清浄なCu表面を得る
事が出来る。Therefore, the oxides are removed by cleaning with an organic solvent such as acetone or trichlene and immersing in a 1 to 10% HCI solution. For example, if immersed in 5% HCI solution for 5 seconds, Cu
A clean Cu surface can be obtained by removing 100 to 200λ from the surface.
又Auメツキ用のメツキ浴として青化物浴,中性リン酸
塩浴,酸性リン酸塩浴,酸性クエン酸浴があるが、本構
成に訃いてはピンホールが少なく、適度の硬度を有する
酸性クエン酸浴が望ましい。In addition, plating baths for Au plating include cyanide baths, neutral phosphate baths, acidic phosphate baths, and acidic citric acid baths. A citric acid bath is preferred.
メツキに際しては、半導体基板11の端部に卦いて、第
2の金寓膜を露出せしめ、これをメツキ用の共通電極と
し、マイナスの電界を加え、一方Pt板等にプラスの電
界を加えれば、電流密度0.4mA/M77lで40〜
60分間に10〜15μmの高さのAuバンプ18を前
記第2の金属膜17の開孔部に形成できる。メツキの形
成が終れば第5の絶縁物層すなわち感 c光性樹脂膜を
除去し、前記Auバンプ18をマスクとして第2の金属
膜17を除去する。When plating, a second metal film is exposed at the end of the semiconductor substrate 11, used as a common electrode for plating, and a negative electric field is applied, while a positive electric field is applied to the Pt plate or the like. , 40~ at current density 0.4mA/M77l
Au bumps 18 with a height of 10 to 15 μm can be formed in the openings of the second metal film 17 in 60 minutes. After the formation of the plating is completed, the fifth insulating layer, that is, the photosensitive resin film is removed, and the second metal film 17 is removed using the Au bumps 18 as a mask.
本構成例に卦いては第2の金属膜がCr−CuC構成さ
れるから、Cu膜を例えば、10%塩化第二鉄溶液で除
去し、Cr膜をフエリシアン化カリウムとNaOHの混
合液で除去するものである。この様にして第2図eの構
造を得る。本発明の構成例に}いては、金属バンプがA
uの場合であつたが、0】 あるいは半田バンプであつ
ても良い。In this configuration example, since the second metal film is composed of Cr-CuC, the Cu film is removed with, for example, a 10% ferric chloride solution, and the Cr film is removed with a mixed solution of potassium ferricyanide and NaOH. It is something. In this way, the structure shown in FIG. 2e is obtained. In the configuration example of the present invention, the metal bump is A
This was the case of u, but it may also be a solder bump.
又、各金属膜間の密着力(付着力)を高め、かつ電気的
接触抵抗を減少させるために例えば300〜550℃で
20〜60分間の熱処理を行えば、金属膜は更に緻密に
なり、かつ合金化が促進され、前述した効果を得る事が
できるものである。本発明の製造方法に訃いては、第2
の金属膜のパターン形成時に腐蝕液が浸透し、パツド電
極近傍まで到達しても前記パツド電極の周縁部の表面上
が耐腐蝕性のAl2O3膜であるために、従来の如くパ
ツド電極の損傷による電気特性の劣化や、金属バンプ強
度の低下を招く事がない。In addition, if heat treatment is performed at 300 to 550°C for 20 to 60 minutes in order to increase the adhesion force (adhesive force) between each metal film and reduce electrical contact resistance, the metal film becomes even more dense. Moreover, alloying is promoted and the above-mentioned effects can be obtained. According to the manufacturing method of the present invention, the second
Even if the corrosive liquid permeates during patterning of the metal film and reaches the vicinity of the pad electrode, the surface of the peripheral edge of the pad electrode is a corrosion-resistant Al2O3 film, so there is no risk of damage to the pad electrode as in the past. It does not cause deterioration of electrical characteristics or decrease in metal bump strength.
参考に第3図Bに前記パツド電極13が部分的に損傷し
た状態を示す。更にバツト電極の一部がAl2O3膜で
あるために前記CVDSiO2膜16はこの部分に}い
て良好な密着力を有するため、CVDSiO2とパツド
電極間に卦ける汚染物質の進行を防止できる等の効果が
ある。For reference, FIG. 3B shows a state in which the pad electrode 13 is partially damaged. Furthermore, since a part of the butt electrode is an Al2O3 film, the CVDSiO2 film 16 has good adhesion to this part, which has the effect of preventing contaminants from advancing between the CVDSiO2 and the pad electrode. be.
第・1図a−eは従来の金属バンプの形成方法を説明す
るための半導体装置の構造断面図、第2図a−eは本発
明の一実施例における金属バンプの形成方法を説明する
ための半導体装置の構造断面図、第3図は本発明の効果
の一例を示すための半導体装置の構造断面図である。
11・・・・・・半導体基板、13・・・・・・パツド
電極、13′・・・・・・Al2O3膜、16・・・・
・・CVDSiO2膜、17・・・・・・第2の金属膜
、18・・・・・・金属バンプ。Figures 1 a-e are structural cross-sectional views of a semiconductor device for explaining a conventional method for forming metal bumps, and Figures 2 a-e are for explaining a method for forming metal bumps in an embodiment of the present invention. FIG. 3 is a structural cross-sectional view of a semiconductor device for illustrating an example of the effects of the present invention. 11... Semiconductor substrate, 13... Pad electrode, 13'... Al2O3 film, 16...
...CVDSiO2 film, 17...second metal film, 18...metal bump.
Claims (1)
程と、前記第1の金属膜上に第1の絶縁物層のパターン
を形成する工程と、前記第1の絶縁物層で被覆されてい
ない前記第1の金属膜の露出表面上に酸化物を形成する
工程と、前記第1の絶縁物層を除去し、前記第1の絶縁
物層パターンの大きさよりも大き目のパターンを有する
第2の絶縁物層を前記第1の金属膜の酸化されていない
部分をおおうように形成する工程と、前記第2の絶縁物
層のパターンをマスクとして、前記第1の金属膜および
前記第1の金属膜表面上の酸化物を除去し、しかる後、
前記第2の絶縁物層を除去する工程と、周縁部表面に前
記酸化物が露出するように前記第1の金属膜面を露出せ
しめた第3の絶縁物層のパターンを形成する工程と、第
2の金属膜を全面に被着せしめ、第4の絶縁物層により
前記第1の金属膜上のみを開孔させたパターンを形成す
る工程と、前記第4の絶縁物層により開孔し露出された
前記第2の金属膜上に金属バンプを形成する工程と、前
記第4の絶縁物層および露出している前記第2の金属膜
を除去する工程とからなる事を特徴とする半導体装置の
製造方法。 2 第1の金属膜がアルミニウム膜で構成される事を特
徴とする特許請求の範囲第1項に記載の半導体装置の製
造方法。[Claims] 1. A step of forming a first metal film for wiring on a semiconductor substrate, a step of forming a pattern of a first insulating layer on the first metal film, and a step of forming a first metal film for wiring on the semiconductor substrate. forming an oxide on the exposed surface of the first metal film not covered with an insulating layer; removing the first insulating layer; forming a second insulating layer having a larger pattern so as to cover the unoxidized portion of the first metal film; and using the pattern of the second insulating layer as a mask, oxides on the surfaces of the metal film and the first metal film are removed, and then,
a step of removing the second insulator layer; and a step of forming a pattern of a third insulator layer in which the first metal film surface is exposed so that the oxide is exposed on the peripheral edge surface; A step of depositing a second metal film on the entire surface and forming a pattern in which holes are formed only on the first metal film using a fourth insulating layer; A semiconductor comprising the steps of: forming a metal bump on the exposed second metal film; and removing the fourth insulating layer and the exposed second metal film. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film is composed of an aluminum film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51072365A JPS5915179B2 (en) | 1976-06-18 | 1976-06-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51072365A JPS5915179B2 (en) | 1976-06-18 | 1976-06-18 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52155050A JPS52155050A (en) | 1977-12-23 |
| JPS5915179B2 true JPS5915179B2 (en) | 1984-04-07 |
Family
ID=13487201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51072365A Expired JPS5915179B2 (en) | 1976-06-18 | 1976-06-18 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5915179B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2796919B2 (en) * | 1992-05-11 | 1998-09-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Metallization composites and semiconductor devices |
-
1976
- 1976-06-18 JP JP51072365A patent/JPS5915179B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52155050A (en) | 1977-12-23 |
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